CY7C1470V25_11 CYPRESS [Cypress Semiconductor], CY7C1470V25_11 Datasheet - Page 10

• Manufacturer Part Number: CY7C1470V25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Truth Table
Partial Write Cycle Description
Document Number: 38-05290 Rev. *L
Deselect cycle
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
Read
Write – no bytes written
Write byte a – (DQ
Write byte b – (DQ
Write bytes b, a
Write byte c – (DQ
Write bytes c, a
Write bytes c, b
Write bytes c, b, a
Write byte d – (DQ
Write bytes d, a
Write bytes d, b
Write bytes d, b, a
Write bytes d, c
Write bytes d, c, a
Write bytes d, c, b
Write all bytes
Notes
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BW
2. Write is defined by WE and BW
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ
8. Table only lists a partial listing of the byte write combinations. Any combination of BW
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
is inactive or when the device is deselected, and DQ
Operation
Function (CY7C1470V25)
[1, 2, 3, 4, 5, 6, 7]
a
b
c
d
and DQP
and DQP
and DQP
and DQP
[a:d]
c
a
d
b
)
)
)
)
. See Write Cycle Description table for details.
Address
External
External
External
Current
Used
None
None
None
None
Next
Next
Next
Next
[1, 2, 3, 8]
s
= data when OE is active.
CE
H
X
X
X
X
X
X
X
L
L
L
L
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
WE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADV/LD WE BW
H
H
H
H
H
X
X
L
L
L
L
L
[a:d]
is valid. Appropriate write will be done based on which byte write is active.
BW
X
X
H
X
H
X
X
X
X
X
L
L
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
x
= L signifies at least one byte write select is active, BW
d
X
X
X
X
X
X
H
H
X
X
L
L
x
OE
X
H
H
X
X
X
X
X
X
L
L
X
BW
LL
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
c
CEN
H
X
L
L
L
L
L
L
L
L
L
L
s
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
and DQP
X
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
b
CY7C1470V25
CY7C1472V25
CY7C1474V25
[a:d]
Data out (Q)
Data out (Q)
Data in (D)
Data in (D)
= tri-state when OE
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
Tri-state
DQ
–
Page 10 of 31
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
x
= valid
a
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