VSC8140QR VITESSE [Vitesse Semiconductor Corporation], VSC8140QR Datasheet - Page 9

• Manufacturer Part Number: VSC8140QR
• Description: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8140
Data Sheet
9/6/00
G52251-0, Rev. 4.0
CLK input. In order to meet jitter transfer, the RXCLK16_32O or RXCLOCK16O needs to be filtered by a 1X
PLL circuit with a narrow pass characteristic. The part is forced out of this mode in Equipment Loopback to
prevent the PLL from feeding its own clock back.
Clock Generator
The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip
loop filter (with two external 0.1 F peaking capacitors). The loop bandwidth of the PLL is within the SONET
specified limit of 2MHz.
REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0” designates REFCLK
input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 2ps RMS of jitter to the output. The
VSC8140 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8140 itself during such
conditions.
Loop Filter
is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connected
between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended
capacitors are low-inductance 0.1 F 0603 ceramic SMT X7R devices with a voltage rating equal to or greater
than 10V.
When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIM-
An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input.
The REFCLK should be of high quality since noise on the REFCLK below the loop bandwidth of the PLL
The PLL on the VSC8140 employs an internal loop filter with off-chip peaking capacitors. The PLL design
The customer can select to provide either a 77.76MHz reference, or 2x of that reference, 155.52MHz.
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Pre-Driver
Figure 13: High-Speed Output Termination
50
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
V
V
EE
CC
50
Transceiver with Integrated Clock Generator
Z
0
= 50
2.48832Gb/s 16:1 SONET/SDH
100
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