VSC8113QB1 VITESSE [Vitesse Semiconductor Corporation], VSC8113QB1 Datasheet

VSC8113QB1

Manufacturer Part Number

VSC8113QB1

Description

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

Manufacturer

VITESSE [Vitesse Semiconductor Corporation]

Datasheet

1.VSC8113QB1.pdf (28 pages)

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VSC8113

G52154-0, Rev 4.2

3/19/99

Data Sheet

Features

General Description

Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel

and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux).

The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains

SONET/SDH frame detection and recovery. The device provides both facility and equipment loopback modes

and two loop timing modes. The part is packaged in a 100PQFP with integrated heat spreader for optimum ther-

mal performance and reduced cost. The VSC8113 provides an integrated solution for ATM physical layers and

SONET/SDH systems applications.

Functional Description

networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8113

converts 8 bit parallel data at 77.76Mb/s or 19Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s respec-

tively. The device also provides a Facility Loopback function which loops the received high speed data and

clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit

(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream

from input reference frequencies of 19.44, 38.88, 51.84 or 77.76 MHz. The CMU can be bypassed with the

received/recovered clock in loop timing mode thus synchronizing the entire part to a single clock. The block

diagram on page 2 shows the major functional blocks associated with the VSC8113.

stream to an 8 bit parallel output at 19.44Mb/s or 77.76MHz respectively. A Clock Recovery Unit (CRU) is inte-

grated into the receive circuit to recover the high speed clock from the received serial data stream. The receive

section provides an Equipment Loopback function which will loop the low speed transmit data and clock back

through the receive section to the 8 bit parallel data bus and clock outputs.The VSC8113 also provides the

option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a

The VSC8113 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication

The VSC8113 is designed to provide a SONET/SDH compliant interface between the high speed optical

The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622Mb/s bit

• Operates at Either STS-3/STM-1 (155.52Mb/s)

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the 155.52MHz

• On Chip Clock Recovery of the 155.52MHz or

• 8 Bit Parallel TTL Interface

• SONET/SDH Frame Recovery

• Lock Detect for both CRU and CMU

or STS-12/STM-4 (622.08Mb/s) Data Rates

or 622.08MHz High Speed Clock (Mux)

622.08MHz High Speed Clock (Demux)

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

VITESSE SEMICONDUCTOR CORPORATION

SEMICONDUCTOR CORPORATION

with Integrated Clock Generation and Clock Recovery

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

• Loss of Signal (LOS) Input & LOS Detection

• +3.3V/5V programmable PECL Serial Interface

• Provides Equipment, Facilities and Split Loop-

• Provide TTL & PECL reference clock inputs

• Meets Bellcore, ITU and ANSI Specifications for

• Low Power - 1.0 Watts Typical

• 100 PQFP Package

back Modes as well as Loop Timing Mode

Jitter Performance

Page 1

Related parts for VSC8113QB1

VSC8113QB1 Summary of contents

Page 1

Data Sheet VSC8113 Features • Operates at Either STS-3/STM-1 (155.52Mb/s) or STS-12/STM-4 (622.08Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 155.52MHz or 622.08MHz High Speed Clock (Mux) • On Chip Clock ...

Page 2

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery CRU clock and data signals. (In this mode the VSC8113 operates just like the VSC8111). The receive section also contains a SONET/SDH frame detector circuit which is used ...

Page 3

Data Sheet VSC8113 Transmit Section Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN. See Figure 1. The data is then serialized (MSB leading) and presented at the TXDATAOUT+/- pins. TXDATAOUT ...

Page 4

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Loss of Signal The VSC8113 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial data stream has no transition continuously for more ...

Page 5

Data Sheet VSC8113 RXDATAIN CRU Recovered Clock RXCLKIN TXDATAOUT TXCLKOUT FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed ...

Page 6

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) and received/recovered clock are mux’d through to the high-speed ...

Page 7

Data Sheet VSC8113 Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi- cated PLL power ...

Page 8

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Clock Recovery The fully monolithic Clock Recovery Unit (CRU) consists of a Phase Detector, a Frequency Detector, a Loop Filter and a Voltage Controlled Oscillator (VCO). The phase ...

Page 9

Data Sheet VSC8113 Jitter Tolerance Jitter Tolerance is the ability of the Clock Recovery Unit to track timing variation in the received data stream. The bellcore and ITU specifications allow the received optical data to contain jitter. The amount that ...

Page 10

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter ...

Page 11

Data Sheet VSC8113 Table 4: Transmit Data Input Timing Table (STS-12 Operation) Parameter T Transmit data input byte clock period CLKIN T Transmit data setup time with respect to TXLSCKIN INSU T Transmit data hold time with respect to TXLSCKIN ...

Page 12

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 7: Receive Data Output Timing Table (STS-3 Operation) Parameter T Receive clock period RXCLKIN T Receive data output byte clock period RXLSCKT Time data on RXOUT [7:0] ...

Page 13

Data Sheet VSC8113 Data Latency The VSC8113 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock signal. Table 10: Data Latency Circuit ...

Page 14

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 13: Clock Multiplier Unit Performance Name RCd Reference clock duty cycle RCj Reference clock jitter (RMS) @ 77.76 MHz ref RCj Reference clock jitter (RMS) @ 51.84 ...

Page 15

Data Sheet VSC8113 DC Characteristics Table 15: PECL and TTL Inputs and Outputs Parameters Description Output HIGH V OH voltage (PECL) Output LOW V OL voltage (PECL) O/P Common V Mode Range OCM (PECL) Differential V Output Voltage OUT75 (PECL) ...

Page 16

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Power Dissipation Table 16: Power Supply Currents Parameter I Power supply current from Power dissipation (worst case) D Absolute Maximum Ratings Power Supply Voltage (V ...

Page 17

Data Sheet VSC8113 Package Pin Description Table 17: Pin Definitions Signal Pin FACLOOP 1 VDD 2 CRUEQLP 3 RESET 4 LOOPTIM0 VDDP 9 TXDATAOUT+ 10 TXDATAOUT- 11 VSS 12 TXCLKOUT+ 13 TXCLKOUT- 14 ...

Page 18

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 17: Pin Definitions Signal Pin VDD 31 N/C 32 RX50MCK 33 VSS 34 RXOUT0 35 RXOUT1 36 VSS 37 RXOUT2 38 RXOUT3 39 VSS 40 RXOUT4 41 ...

Page 19

Data Sheet VSC8113 Table 17: Pin Definitions Signal Pin CN1 64 CN2 65 CP2 66 VDDA 67 VDDA 68 VDDA 69 VSSA 70 VSSA 71 VSS 72 N CRULOCKDET VSS 75 VDD 76 N/C 77 N/C 78 N/C ...

Page 20

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Table 17: Pin Definitions Signal Pin STS12 97 CRUREFSEL 98 VDD 99 EQULOOP 100 Page 20 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE ...

Page 21

Data Sheet VSC8113 Package Information PIN 100 PIN 1 EXPOSED HEATSINK (NOTE 2) 9.0 X 9.0 (N0TE 2) PIN NOTES: (1) Drawings not to scale. (2) Two styles of exposed heat spreaders may be used; square or ...

Page 22

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery The VSC8113 is manufactured in a 100PQFP package which is supplied by two different vendors. The crit- ical dimensions in the drawing represent the superset of dimensions for ...

Page 23

... Part Number Device Type VSC8113QB: 155/622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Commercial Temperature ambient case VSC8113QB1 155/622Mb/s Mux/Dmux with CMU and CRU in 100 Pin PQFP Extended Temperature ambient (equivalent ambient to 115 C case) VSC8113QB2 ...

Page 24

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Application Notes Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8113 has been brought off-chip to allow as much flexibility in ...

Page 25

Data Sheet VSC8113 Important note: The 11 ns max Tpd on the PM5355 assumes a 50pf load @ 60ps/pf, therefore the max delay is due to loading. The VSC8113 input (TXLSCKIN) plus package is about 6pf. Assuming ...

Page 26

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Layout of the High Speed Signals The routing of the High Speed signals should be done using good high speed design practices. This would include using controlled impedance ...

Page 27

Data Sheet VSC8113 V +3 INPUT R GND REFCLK and TTL Inputs G52154-0, Rev 4.2 3/19/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock ...

Page 28

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Page 28 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8113 G52154-0, Rev 4.2 3/19/99 ...

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