VSC8140QR VITESSE [Vitesse Semiconductor Corporation], VSC8140QR Datasheet - Page 4

• Manufacturer Part Number: VSC8140QR
• Description: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

Transceiver with Integrated Clock Generator
2.48832Gb/s 16:1 SONET/SDH
Page 4
Receiver Low-Speed Interface
RXOUT[15:0] with accompanying differential LVPECL divide-by-16 clock RXCLK16O ± and selectable
LVPECL divide-by-16 or -32 clock RXCLK16_32O ± .
RXCLK16_32O ± output as 77.76MHz, RXCLKO_FREQSEL = “1” designates RXCLK16_32O ± output as
155.52MHz.
transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by
50
illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for
AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can
be used to provide an external looptiming reference clock (after external filtering with a 1x REFCLK PLL) for
the clock multiplication unit on the VSC8140.
nated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7).
Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs
The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface
The RXCLK16O and RXCLK16_32O output drivers are designed to drive a 50
The RXOUT[15:0] output drivers are designed to drive a 50
RXCLKO_FREQSEL is used to select RXCLK16_32O ± . RXCLKO_FREQSEL = “0” designates
to V
VSC8140
CC
Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
-2V on each line (see Figure 4). AC-coupling can be achieved by a number of methods. Figure 5
VSC8140
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
VITESSE
SEMICONDUCTOR CORPORATION
VITESSE SEMICONDUCTOR CORPORATION
Split-end equivalent termination is Z
R1 = 125
V
CC
R1||R2 = Z
R2 + V
R1+R2
Z
Z
o
R2 = 83 , Z
o
EE
o
R1
50
= V
O
=50 , V
TERM
TERM
O
Z
to V
o
= V
50
V
transmission line which can be DC termi-
TERM
CC
CC
-2V
-2V
100nF
100nF
R1 = 125
R2 = 83
V
CC
V
EE
downstream
transmission line. The
bias point
generated
internally
VSC8140
Data Sheet
G52251-0, Rev. 4.0
9/6/00