VSC8140QR VITESSE [Vitesse Semiconductor Corporation], VSC8140QR Datasheet - Page 13

• Manufacturer Part Number: VSC8140QR
• Description: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8140
Data Sheet
9/6/00
G52251-0, Rev. 4.0
Supplies
use the device in an ECL environment with a negative 3.3V supply, then V
3.3V. If used with V
recommended that the V
on each V
also be placed in parallel with the 0.1 F and 0.01 F capacitors mentioned above. Recommended capacitors are
low-inductance ceramic SMT X7R devices. For the 0.1 F capacitor, a 0603 package should be used. The
0.01 F and 0.001 F capacitors can be either 0603 or 0403 packages.
maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8140, the analog
power supply pins should be filtered from the main power supply with a 10 H C-L-C pi filter. If preferred, a
ferrite bead may be used to provide the isolation. The 0.1 F and 0.01 F decoupling capacitors are still required
and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).
main +3.3V power supply and placed close to the C-L-C pi filter.
V
CC
The VSC8140 is specified as a PECL device with a single positive 3.3V supply. Should the user desire to
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
Extra care needs to be taken when decoupling the analog power supply pins (labeled V
For low frequency decoupling, 47 F tantalum low-inductance SMT caps are sprinkled over the board’s
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
must be changed to V
CC
power supply pin as close to the package as possible. If room permits, a 0.001 F capacitor should
EE
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
tied to -3.3V, the TTL control signals are still referenced to V
V
CC
0.1 F
EE
EE
Figure 17: PLL Power Supply Decoupling Scheme
power supply be decoupled using a 0.1 F and 0.01 F capacitor placed in parallel
, and all references to decoupling 3.3V must be changed to -3.3V.
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
V
SEMICONDUCTOR CORPORATION
Note: V
CC
10 H
0.1 F
CC
V
can be tied to V
CCANA
Transceiver with Integrated Clock Generator
V
CCANA
CCANA
0.01 F
V
CC
2.48832Gb/s 16:1 SONET/SDH
EEANA
will be ground and V
EE
.
CCANA
). In order to
EE
will be -
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