VSC8140QR VITESSE [Vitesse Semiconductor Corporation], VSC8140QR Datasheet - Page 5

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VSC8140QR

Manufacturer Part Number
VSC8140QR
Description
2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet

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VSC8140QR
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VSC8140
Data Sheet
9/6/00
G52251-0, Rev. 4.0
ever, DC-coupling is preferred since there is no guarantee of transition density for individual bits in the 16-bit
word. Figure 8 illustrates an AC-coupling method for the occasion when the downstream device provides the
bias point for AC-coupling. Figure 9 illustrates an AC-coupling method for the occasion when the bias point
needs to be generated externally. The resistor values in Figure 9 were selected to generate a bias point of 1.98V,
the mid-point for LVPECL V
generate the necessary bias point for the downstream device.
The RXOUT[15:0] output drivers can also be appropriately AC-coupled by a number of methods, how-
VSC8140
Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
VSC8140
Figure 8: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
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OH
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and V
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
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as specified for the VSC8140. Resistor values should be selected to
Z
o
Transceiver with Integrated Clock Generator
Z
o
R1 = 50
V
CC
2.48832Gb/s 16:1 SONET/SDH
-2V
R1 =50
V
CC
100nF
-2V
downstream
bias point
generated
internally
Page 5

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