CY7C1412AV18-250BZXI CYPRESS [Cypress Semiconductor], CY7C1412AV18-250BZXI Datasheet - Page 9

• Manufacturer Part Number: CY7C1412AV18-250BZXI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05615 Rev. *D
Application Example
Truth Table
Write Cycle Descriptions
Write Cycle:
Load address on the rising edge of K clock; input
write data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
Notes:
BWS
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
3. Device powers up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 00, A + 01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
8. Assumes a Write cycle was initiated according to the Write Port Cycle Description Truth Table. NWS
MASTER
charging symmetrically.
on different portions of a Write cycle, as long as the setup and hold requirements are achieved.
ASIC)
BUS
(CPU
or
0
L
L
L
/ NWS
CLKIN/CLKIN#
Delayed K#
DATA OUT
0
Delayed K
Source K#
Source K
DATA IN
[2, 3, 4, 5, 6, 7]
Address
BWS
BWS#
WPS#
RPS#
1
Operation
H
L
L
/ NWS
Vt
R
R
[1]
1
R = 50οηµσ
L-H
L-H
K
(CY7C1410AV18 and CY7C1412AV18)
–
D
A
L-H
K
Vt = Vddq/2
–
–
↑
R
P
#
S
represents rising edge.
W
SRAM #1
P
S
#
During the data portion of a write sequence:
CY7C1410AV18 − both nibbles (D
CY7C1412AV18 − both bytes (D
During the data portion of a write sequence:
CY7C1410AV18 − both nibbles (D
CY7C1412AV18 − both bytes (D
During the data portion of a write sequence:
CY7C1410AV18 − only the lower nibble (D
remains unaltered,
CY7C1412AV18 − only the lower byte (D
remains unaltered.
W
B
#
S
Stopped
C C#
L-H
L-H
L-H
K
CQ/CQ#
K
ZQ
K#
Q
R = 250οηµσ
RPS
X
H
X
L
[2, 8]
WPS
X
H
X
L
[17:0]
[17:0]
Comments
[7:0]
[7:0]
0
, NWS
D(A + 0) at K(t) ↑
Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑
Q = High-Z
Previous State
D = X
D
A
) are written into the device.
) are written into the device.
) are written into the device,
) are written into the device,
[8:0]
R
1
, BWS
[3:0]
) is written into the device. D
Vt
Vt
) is written into the device. D
DQ
0
R
P
#
S
, BWS
W
SRAM #4
P
S
#
W
B
#
S
1
, BWS
CY7C1410AV18
CY7C1425AV18
CY7C1412AV18
CY7C1414AV18
C C#
2
D(A + 1) at K(t) ↑
D = X
Q = High-Z
Previous State
and BWS
CQ/CQ#
K
ZQ
K#
Q
3
Page 9 of 25
DQ
can be altered
R = 250οηµσ
[17:9]
[7:4]