CY7C1412AV18-250BZXI CYPRESS [Cypress Semiconductor], CY7C1412AV18-250BZXI Datasheet
CY7C1412AV18-250BZXI
Related parts for CY7C1412AV18-250BZXI
CY7C1412AV18-250BZXI Summary of contents
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... Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit words (CY7C1412AV18) or 36-bit words (CY7C1414AV18) that burst sequentially into or out of the device. While data can be transferred into and out of the device on every rising edge ...
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... Reg Register Control Logic Read Data Reg Reg. Reg. 8 Reg. Write Write Address Reg Reg Register Control Logic Read Data Reg. 18 Reg. Reg. 9 Reg. 9 CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 A (20:0) 21 RPS [7: (20:0) 21 RPS [8:0] 9 Page ...
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... Logic Block Diagram (CY7C1412AV18) D [17:0] 18 Address Register A (19: CLK K Gen. DOFF V REF WPS Control Logic BWS [1:0] Logic Block Diagram (CY7C1414AV18) D [35:0] 36 Address Register A (18: CLK K Gen. DOFF V REF WPS Control Logic BWS [3:0] Document #: 38-05615 Rev. *D Write Write Address Reg Reg Register ...
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... V V DDQ DDQ CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 RPS DDQ DDQ ...
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... DDQ J D31 Q31 D23 K Q32 D32 Q23 L Q33 Q24 D24 M Q34 D33 D25 N D34 D26 Q25 P Q35 D35 Q26 R TDO TCK A Document #: 38-05615 Rev. *D CY7C1412AV18 ( WPS BWS K NC/288M BWS ...
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... Read and Write operations. Internally, the device is organized arrays each for CY7C1410AV18 arrays each for CY7C1425AV18 arrays each 18) for CY7C1412AV18 and arrays each of 512K x 36) for CY7C1414AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1410AV18 and CY7C1425AV18, 20 address inputs for CY7C1412AV18 and 19 address inputs for CY7C1414AV18 ...
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... Each access consists of two 8-bit data transfers in the case of CY7C1410AV18, two 9-bit data transfers in the case of CY7C1425AV18,two 18-bit data transfers in the case of CY7C1412AV18 and two 36-bit data transfers in the case of CY7C1414AV18, in one clock cycle. Document #: 38-05615 Rev. *D CY7C1410AV18 ...
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... Write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1412AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). ...
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... During the data portion of a write sequence: CY7C1410AV18 − both nibbles (D CY7C1412AV18 − both bytes (D [17:0] – During the data portion of a write sequence: CY7C1410AV18 − only the lower nibble (D remains unaltered, CY7C1412AV18 − only the lower byte (D remains unaltered. ↑ represents rising edge. CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 SRAM # 250ο ...
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... L-H During the data portion of a write sequence: CY7C1410AV18 − only the upper nibble (D remains unaltered, CY7C1412AV18 − only the upper byte (D remains unaltered. – No data is written into the devices during this portion of a write operation. L-H No data is written into the devices during this portion of a write operation. ...
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... This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Document #: 38-05615 Rev. *D CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Upon power up, the instruction register is loaded with the IDCODE instruction also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section ...
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... Document #: 38-05615 Rev. *D CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05615 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... Boundary Scan Register TAP Controller [15, 18, 10] Over the Operating Range Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Selection Circuitry TDO Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 ...
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... Test conditions are specified using the load in TAP AC test conditions. t Document #: 38-05615 Rev. *D [11, 12] Over the Operating Range Description [12] 1. TMSS t TMSH t TDIS t TDIH t TDOV / ns CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Min Max Unit MHz ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 CY7C1414AV18 Description 000 Version number. SRAM. ...
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... CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Bit # Bump 100 ...
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... If the input clock is unstable and the DLL is enabled, then the DLL may lock to an incorrect frequency, causing unstable SRAM behavior REF > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tied to V DDQ ) CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 . KC Var . Start Normal Operation Page ...
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... RQ <= 350Ωs. /2), Undershoot: V (AC) > –1.5V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 [18] ............................... –0. 0.3V DD Ambient [19] [19 DDQ 1.8 ± 0.1V 1. ...
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... R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω (b) /I and load capacitance shown in ( Test Loads CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 165 FBGA Package Unit °C/W 17.2 °C/W 3.2 [22] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ns = 1.5V, input DDQ Page ...
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... CLZ CHZ CO is the time that the power needs to be supplied above V is 0.5 ns for 200 MHz, and 250 MHz frequencies. SD CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 200 MHz 167 MHz Min Max Min Max Unit 6.3 5.0 7.9 6.0 8.4 – ...
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... CYC t KHKH D31 D50 D51 D60 Q00 Q01 Q20 t CQDOH t DOH t CYC t CCQO t CQOH t CCQO CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 WRITE NOP D61 Q21 Q40 Q41 t CHZ t CQD DON’T CARE UNDEFINED Page ...
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... CY7C1410AV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1425AV18-200BZI CY7C1412AV18-200BZI CY7C1414AV18-200BZI CY7C1410AV18-200BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1425AV18-200BZXI CY7C1412AV18-200BZXI CY7C1414AV18-200BZXI 250 CY7C1410AV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) CY7C1425AV18-250BZC CY7C1412AV18-250BZC CY7C1414AV18-250BZC CY7C1410AV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... CY7C1412AV18-250BZI CY7C1414AV18-250BZI CY7C1410AV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1425AV18-250BZXI CY7C1412AV18-250BZXI CY7C1414AV18-250BZXI Package Diagram 165-Ball FBGA ( 1.40 mm) (51-85195) QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung technology ...
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... Document History Page Document Title: CY7C1410AV18/CY7C1425AV18/CY7C1412AV18/CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture Document Number: 38-05615 REV. ECN No. Issue Date ** 247331 See ECN *A 326519 See ECN *B 413953 See ECN *C 468029 See ECN *D 1274725 See ECN VKN/AESA Modified footnote# 30 Document #: 38-05615 Rev. *D Orig ...