CY7C1412AV18-250BZI Cypress Semiconductor Corporation., CY7C1412AV18-250BZI Datasheet

CY7C1412AV18-250BZI

Manufacturer Part Number

CY7C1412AV18-250BZI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1412AV18-167BZXC.pdf (25 pages)

2.CY7C1412AV18-167BZXC.pdf (25 pages)

Specifications of CY7C1412AV18-250BZI

Package

BGA

Date_code

09+

Current page: 1 of 25
Download datasheet (2Mb)

Cypress Semiconductor Corporation

Document #: 38-05615 Rev. *D

Features

Configurations

CY7C1410AV18 – 4M x 8

CY7C1425AV18 – 4M x 9

CY7C1412AV18 – 2M x 18

CY7C1414AV18 – 1M x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

• Separate Independent Read and Write data ports

• 250-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and Write

• Two input clocks (K and K) for precise DDR timing

• Two input clocks for output data (C and C) to minimize clock

• Echo clocks (CQ and CQ) simplify data capture in

• Single multiplexed address input bus latches address inputs

• Separate Port Selects for depth expansion

• Synchronous internally self timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

• Core V

• Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both Pb-free and non Pb-free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

— Supports concurrent transactions

ports (data transferred at 500 MHz) @ 250 MHz

— SRAM uses rising edges only

skew and flight-time mismatches

high-speed systems

for both Read and Write ports

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

•

198 Champion Court

36-Mbit QDR-II™ SRAM 2-Word Burst

250 MHz

1065

250

Functional Description

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and

CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common IO

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

the rising edge of the K clock. Accesses to the QDR-II Read

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit

words (CY7C1412AV18) or 36-bit words (CY7C1414AV18)

that burst sequentially into or out of the device. While data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self timed write circuitry.

•

San Jose

200 MHz

200

870

CA 95134-1709

Revised July 09, 2007

167 MHz

CY7C1410AV18

CY7C1425AV18

CY7C1412AV18

CY7C1414AV18

167

740

Architecture

•

408-943-2600

Unit

MHz

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