CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Burst Sequences
This family of devices provide a 2-bit wrap-around burst
counter inside the SRAM. The burst counter is fed by A
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
Address
A
X + 1
First
00
01
10
11
, A
x
Address
A
Second
X + 1
01
00
11
10
, A
x
Address
A
Third
X + 1
10
11
00
01
, A
x
Address
A
Fourth
X + 1
11
10
01
00
, A
[1:0]
x
,
5
Table 2. Counter Implementation for a Linear Sequence
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Ac-
cesses pending when entering the “sleep” mode are not con-
sidered valid nor is the completion of the operation guaran-
teed. The device must be deselected prior to entering the
“sleep” mode. CE
inactive for the duration of t
LOW.
Address
A
X + 1
First
00
01
10
11
, A
x
1
, CE
Address
A
Second
X + 1
01
10
11
00
2
, CE
, A
x
3
ZZREC
, ADSP, and ADSC must remain
Address
A
after the ZZ input returns
X + 1
Third
10
11
00
01
, A
x
CY7C1325
Address
A
Fourth
X + 1
11
00
01
10
, A
x