CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 12

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing Diagrams
ADV
ADSC
ADSP
Data
In/Out
Read/Write Cycle Timing
CE
CE
OE
WE
ADD
CLK
1
Device originally
deselected
t
t
CLZ
CDV
A
CE is the combination of CE
WE is the combination of BWE, BWS
Qx stands for Data-out X.
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
t
t
ADS
AS
t
t
CES
CES
Q(A)
(continued)
B
t
ADS
t
AH
Q(B)
t
ADVS
(B+1)
Q
2
and CE
ADSP ignored
with CE
(B+2)
t
CH
Q
t
ADVH
[1:0]
3
. All chip selects need to be active in order to select
1
(B+3)
HIGH
Q
, and GW to define a write cycle (see Write Cycle Descriptions table).
t
t
CYC
ADH
Q(B)
12
t
WES
t
EOHZ
D(C)
C
t
CL
t
t
CEH
ADH
t
(C+1)
CEH
D
t
DOH
t
WEH
(C+2)
D
(C+3)
t
D
CHZ
D
CY7C1325
Q(D)