CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pin Descriptions
85
84
36, 37
50–44,
80–82, 99,
100, 32–35
94, 93
83
87
88
89
98
97
92
86
64
31
23, 22, 19,
18, 13, 12, 9,
8, 73, 72, 69,
68, 63, 62,
59, 58
74, 24
15, 41, 65,
91
Pin Number
ADSC
ADSP
A
A
BWS
ADV
BWE
GW
CLK
CE
CE
CE
OE
ZZ
MODE
DQ
DP
V
Name
[1:0]
[17:2]
DD
1
2
3
[1:0]
[15:0]
[1:0]
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O-
I/O-
I/O
-
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE
A
well as being used to access a particular memory location in the memory array.
Address Inputs used in conjunction with A
locations. Sampled at the rising edge of the CLK, if CE
active, and ADSP or ADSC is active LOW.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BWS
and DP
Advance input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
used to conduct a global write, independent of the state of BWE and BWS
writes override byte writes.
Clock input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-pow-
er standby mode in which all other inputs are ignored, but the data in the memory
array is maintained. Leaving ZZ floating or NC will default the device into an active
state. ZZ has an internal pull down.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull up.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
ically three-stated when a WRITE cycle is detected.
Bidirectional Data Parity lines. These behave identical to DQ
These signals can be used as parity bits for bytes 0 and 1 respectively.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
1
, A
[15:0]
0
address inputs, These inputs feed the on-chip burst counter as the LSBs as
[17:0]
[17:0]
1
. See Write Cycle Descriptions table for further details.
and DP
is captured in the address registers. A
is captured in the address registers. A
[1:0]
3
1
2
1
1
are placed in a three-state condition. The outputs are automat-
is deasserted HIGH.
and CE
and CE
and CE
3
3
2
to select/deselect the device.
to select/deselect the device. CE
to select/deselect the device.
0
controls DQ
Description
[17:0]
during the previous clock rise of the read
[1:0]
to select one of the 256K address
[7:0]
[1:0]
[1:0]
and DP
1
are also loaded into the burst
are also loaded into the burst
, CE
0
, BWS
2
, and CE
[15:0]
1
1
gates ADSP.
described above.
controls DQ
CY7C1325
3
are sampled
[1:0]
. Global
[15:8]