CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 13

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing Diagrams
ADV
ADSC
Pipeline Timing
ADSP
Data
CE
CE
OE
WE
ADD
CLK
1
Device originally
deselected
t
t
CLZ
CDV
A
CE is the combination of CE
Qx stands for Data-out X.
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
t
t
ADS
AS
Q(A)
B
(continued)
t
CES
Q(B)
C
Q(C)
D
Q(D)
2
= DON’T CARE
and CE
ADSP ignored
with CE
t
CH
3
. All chip selects need to be active in order to select
1
HIGH
t
t
CYC
ADH
13
= UNDEFINED
t
WES
E
t
t
CEH
CL
D (E)
F
t
DOH
t
WEH
D (F)
G
D (G)
H
t
CHZ
D (H)
D(C)
CY7C1325