CY7C1325-50AC CYPRESS [Cypress Semiconductor], CY7C1325-50AC Datasheet - Page 11

• Manufacturer Part Number: CY7C1325-50AC
• Description: 256K x 18 Synchronous 3.3V Cache RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Timing Diagrams
Read Cycle Timing
Note:
16. RDx stands for Read Data from Address X.
WE
Data Out
CLK
ADSP
ADSC
ADV
ADD
GW
CE
CE
OE
CE
2
3
1
t
t
t
CES
CES
ADS
t
AS
t
CES
RD1
t
t
ADVS
Single Read
CDV
t
t
CEH
EOV
t
t
CYC
[14, 16]
CEH
t
t
t
t
(continued)
CEH
ADH
AH
WS
1a
1a
t
ADS
t
t
WH
ADVH
t
OEHZ
RD2
t
CLZ
t
CH
t
ADH
t
= DON’T CARE
CL
2a
t
DOH
t
WS
Burst Read
2b
t
WH
11
ADSP ignored with CE
Suspend Burst
= UNDEFINED
2c
CE
2c
1
masks ADSP
ADSC initiated read
Pipelined Read
RD3
1
2d
inactive
Unselected with CE
3a
t
CHZ
Unselected
CY7C1325
2