S29PL032J SPANSION [SPANSION], S29PL032J Datasheet - Page 26

• Manufacturer Part Number: S29PL032J
• Description: CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
• Manufacturer: SPANSION [SPANSION]

24
Standby Mode
Automatic Sleep Mode
I
the write mode. See the timing specification tables and timing diagrams in the
"Reset" section for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This
function is primarily intended to allow faster manufacturing throughput at the
factory.
If the system asserts V
mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V
turns the device to normal operation. Note that V
WP#/ACC for operations other than accelerated programming, or device damage
may result. In addition, the WP#/ACC pin should be raised to V
use. That is, the WP#/ACC pin should not be left floating or unconnected; incon-
sistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Standard
read cycle timings apply in this mode. Refer to the
section and
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in
PL129J) and RESET# pins are both held at V
restricted voltage range than V
are held at V
but the standby current will be greater. The device requires standard access time
(t
it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
ICC3 in
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at V
the device reduces current to the stated sleep mode specification. ICC5 in
Characteristics”
CC2
CE
) for read access when the device is in either of these standby modes, before
in the DC Characteristics table represents the active current specification for
“DC Characteristics”
"Autoselect Command
IH
, but not within V
represents the automatic sleep mode current specification.
S29PL127J/S29PL129J/S29PL064J/S29PL032J
HH
on this pin, the device automatically enters the afore-
represents the CMOS standby current specification.
IO
IH
.) If CE# (CE1#,CE#2 in PL129J) and RESET#
± 0.3 V, the device will be in the standby mode,
Sequence" section for more information.
P R E L I M I N A R Y
IO
± 0.3 V. (Note that this is a more
HH
HH
"SecSiTM Sector
from the WP#/ACC pin re-
must not be asserted on
CC
when not in
Addresses"
IH
before
ACC
“DC
+
31107A62 April 7, 2005