S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet - Page 50

• Manufacturer Part Number: S29PL-N_07
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

9.
9.1
9.2
9.3
9.4
50
Power Conservation Modes
Standby Mode
Automatic Sleep Mode
Hardware RESET# Input Operation
Output Disable (OE#)
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#
inputs are both held at V
is ready to read data. If the device is deselected during erasure or programming, the device draws active
current until the operation is completed. I
specification
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the
device automatically enables this mode when addresses remain stable for t
mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is latched and always available to
the system. I
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
all outputs, resets the configuration register, and ignores all read/write commands for the duration of the
RESET# pulse. The device also resets the internal state machine to reading array data. The operation that
was interrupted should be reinitiated once the device is ready to accept another command sequence to
ensure data integrity.
When RESET# is held at V
V
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
When the OE# input is at V
impedance state.
IL
but not within V
CC6
in
SS
DC Characteristics on page 57
±0.2 V, the standby current is greater.
CC
SS
IH
±0.2 V. The device requires standard access time (t
, output from the device is disabled. The outputs are placed in the high
S29PL-N MirrorBit
±0.2 V, the device draws CMOS standby current (I
D a t a
RP
, the device immediately terminates any operation in progress, tristates
CC3
S h e e t
in
DC Characteristics on page 57
™
Flash Family
represents the automatic sleep mode current specification.
( P r e l i m i n a r y )
ACC
represents the standby current
+ 20 ns. The automatic sleep
CE
S29PL-N_00_A5 June 6, 2007
CC4
) for read access, before it
). If RESET# is held at