MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 360

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

Analog-to-Digital Converter
Technical Data
360
AFFC — ATD Fast Conversion Complete Flag Clear
ASWAI — ATD Stop In Wait Mode
This bit provides program on/off control over the ATD module allowing
reduced MCU power consumption when the ATD is not being used.
When reset to zero, the ADPU bit aborts any conversion sequence in
progress. Because the analog electronics is turned off when powered
down, the ATD requires a recovery time period when ADPU bit is
enabled.
Operating normally means that the status register must be read after
the conversion complete flag has been set before that flag can be
reset. After the status register read, a read to the associated result
register causes its conversion complete flag in the status register to be
cleared. The SCF flag is cleared when a new conversion sequence is
begun by writing to control register ATDCTL4/5. In applications where
the ATD module is polled to determine if an ATD conversion is
complete, this feature provides a convenient way of clearing the status
register conversion complete flag.
In applications where ATD interrupts are used to signal conversion
completion, the precondition of reading the status register can be
eliminated using fast conversion complete flag clear mode. In this
mode, any access to a result register will cause its associated
conversion complete flag in the status register to be cleared. The SCF
flag is cleared after the first (any) result register is read.
The wait function allows the MCU to selectively halt and power down
the ATD module. If the ASWAI bit is set and the MCU, then the ATD
module immediately halts operation and powers down. When WAIT is
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0 = ATD flag clearing operates normally (read the status register
1 = Changes all ATD conversion complete flags to a fast clear
0 = ATD continues to run when the MCU is in wait mode
1 = ATD stops to save power when the MCU is in wait mode
before reading the result register to clear the associated CCF
bit).
sequence. Any access to a result register (ATD0–7) will cause
the associated CCF flag to clear automatically if it was set at
the time.
Analog-to-Digital Converter
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MC68HC912D60A — Rev 3.0
MOTOROLA