MC68HC912D60 Motorola, MC68HC912D60 Datasheet - Page 158

• Manufacturer Part Number: MC68HC912D60
• Description: Microcontrollers
• Manufacturer: Motorola

Clock Functions
PLLCR — PLL Control Register
Technical Data
158
1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low.
2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low.
RESET:
LOCKIE
Bit 7
0
PLLON
—
6
(1)
Read and write anytime. Exceptions are listed below for each bit.
LOCKIE — PLL LOCK Interrupt Enable
PLLON — Phase Lock Loop On
AUTO — Automatic Bandwidth Control
Forced to 0 when VDDPLL=0.
Cannot be cleared when BCSP = 1 (PLL selected as bus clock).
Forced to 0 when VDDPLL is at VSS level. In limp-home mode, the
output of PLLON is forced to 1, but the PLLON bit reads the latched
value.
Automatic bandwidth control selects either the high bandwidth
(acquisition) mode or the low bandwidth (tracking) mode depending
on how close to the desired frequency the VCO is running. See
Electrical
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = PLL LOCK interrupt is disabled
1 = PLL LOCK interrupt is enabled
0 = Turns the PLL off.
1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will
0 = Automatic Mode Control is disabled and the PLL is under
1 = Automatic Mode Control is enabled. ACQ bit is read only.
AUTO
5
1
lock automatically.
software control, using ACQ bit.
Specifications.
Go to: www.freescale.com
ACQ
Clock Functions
4
0
3
0
0
PSTP
2
0
LHIE
MC68HC912D60A — Rev 3.0
1
0
NOLHM
Bit 0
—
(2)
MOTOROLA
$003C