IDT7132 Integrated Device Technology, IDT7132 Datasheet - Page 11

• Manufacturer Part Number: IDT7132
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

IDT
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
ORDERING INFORMATION
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAM the busy
pin is an output if the part is used as a master (M/
and the busy pin is an input if the part used as a slave (M/
= V
BUSY
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and IDT7142 (Slave) RAMs.
IL
R/
Device Type
) as shown in Figure 4.
W
XXXX
LEFT
270
+5V
Power
R/
BUSY
R/
BUSY
W
W
A
MASTER
IDT7132
IDT7142
IDT7142
SLAVE
SLAVE
Speed
999
(1)
BUSY
BUSY
R/
R/
+5V
W
W
Package
270
A
RIGHT
2692 drw 15
Temperature
R/
BUSY
S
W
Process/
pin = V
Range
A
S
IH
pin
),
6.02
Blank
B
P
C
J
L48
F
20
25
35
55
100
LA
SA
7132
7142
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
Commercial (0 C to +70 C)
Military (–55 C to +125 C)
Compliant to MIL-STD-883, Class B
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
Commercial PLCC Only
Low Power
Standard Power
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W
signal or the byte enables. Failure to
Speed in nanoseconds
2692 drw 16
11