IDT7132 Integrated Device Technology, IDT7132 Datasheet - Page 10

• Manufacturer Part Number: IDT7132
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

TABLE I — NON-CONTENTION
READ/WRITE CONTROL
NOTES:
1. A
2. If
3. If
4. 'H' = V
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
TABLE II — ADDRESS BUSY ARBITRATION
TRUTH TABLES
NOTES:
1. Pins
2. 'L' if the inputs to the opposite port were stable prior to the address and
3. Writes to the left port are internally ignored when
R/
CE CE CE CE CE
H
H
X
X
L
X
H
X
L
W W W W W CE CE CE CE CE
0L
inputs for IDT7140 (slave).
drain, not push-pull outputs. On slaves the
writes.
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
not be low simultaneously.
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.
BUSY
BUSY
L
Left or Right Port
– A
BUSY
IH
H
H
L
L
L
BUSY
10L
CE CE CE CE CE
, 'L' = V
= L, data is not written.
= L, data may not be valid, see t
X
X
H
L
Inputs
R
L
L
A
and
OE
OE OE
OE OE
H
X
X
X
L
or
0R
NO MATCH
IL
A
A
, 'X' = DON’T CARE, 'Z' = High-impedance.
BUSY
MATCH
MATCH
MATCH
0R
BUSY
0L
– A
DATA
-A
-A
DATA
10R
D
10L
10R
R
R
(1)
0–7
Z
Z
Z
= Low will result.
.
are both outputs for IDT7130 (master). Both are
OUT
IN
BUSY
BUSY
BUSY
BUSY
BUSY
BUSY
Port Disabled and in Power-
Down Mode, I
CE
Mode, I
Data Written Into Memory
Data in Memory Output on Port
High Impedance Outputs
(2)
BUSY
H
H
H
R
X
L
(4)
Outputs
(1)
=
outputs on the IDT7130 are open
R
CE
WDD
SB1
outputs are driving Low regard-
BUSY
BUSY
BUSY
BUSY
BUSY
BUSY
BUSY
L
=
or I
and t
(2)
Function
H
H
H
V
L
SB2
IH
SB3
R
X
and
DDD
, Power-Down
(1)
input internally inhibits
or I
BUSY
BUSY
timing.
Normal
Normal
Normal
Write Inhibit
SB4
Function
L
R
outputs are
outputs can
(2)
2654 tbl 13
2654 tbl 12
(3)
(3)
6.02
FUNCTIONAL DESCRIPTION
The IDT7132/IDT7142 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT7132/
IDT7142 has an automatic power down feature controlled by
CE
permits the respective port to go into a standby mode when
not selected (
entire memory array is permitted.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
in slave mode with the M/
BUSY
operation can be programmed by tying the
If desired, unintended write operations can be prevented to
a port by tying the busy pin for that port low.
The busy outputs on the IDT7132/IDT7142 RAM in master
mode, are pull-up type outputs and do not require pull up
resistors to operate. If these RAMs are being expanded in
depth, then the busy indication for the resulting array re-
quires the use of an external AND gate.
. The
pin operates solely as a write inhibit input pin. Normal
CE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CE
controls on-chip power down circuitry that
=
V
IL
). When a port is enabled, access to the
S
pin. Once in slave mode the
BUSY
pins High.
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