IDT7132 Integrated Device Technology, IDT7132 Datasheet - Page 9

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IDT7132

Manufacturer Part Number
IDT7132
Description
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
Manufacturer
Integrated Device Technology
Datasheet

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IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF WRITE WITH
NOTES:
1. t
2.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'.
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING
NOTES:
1. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'.
2. If t
ADDR
ADDR
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY
BUSY
BUSY
WH
'A'
BUSY
ADDR
APS
and
must be met for both
CE
CE
'B'
'A'
'B'
is asserted on port 'B' blocking R/
is not satisified, the
'B'
'A'
'A'
'B'
t
APS
(2)
BUSY
BUSY
BUSY
R/
Input (IDT7142, slave) or Output (IDT7132, master).
R/
will be asserted on one side or the other, but there is no guarantee on which side
t
W
APS
W
R
R
L
(2)
W
ADDRESSES MATCH
'B', until
t
BAA
t
RC
BUSY
t
BAC
or t
t
WB
WC
'B' goes High.
BUSY
BUSY
BUSY
BUSY
BUSY
(3)
ADDRESSES MATCH
(2)
6.02
t
WP
t
BDC
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESSES DO NOT MATCH
t
WH
t
BDA
2692 drw 12
(1)
CE CE CE CE CE
TIMING
BUSY
will be asserted (7132 only).
(1)
2692 drw 14
2692 drw 13
(1)
9

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