IDT7132 Integrated Device Technology, IDT7132 Datasheet - Page 7

• Manufacturer Part Number: IDT7132
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
NOTES:
1. R/
2. A write occurs during the overlap (t
3. t
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the
6. Timing depends on which enable signal (
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
8. If
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/
ADDRESS
DATA
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
DATA
with the Output Test Load (Figure 2).
data to be placed on the bus for the required t
write pulse can be as short as the specified t
WR
W
OE
ADDRESS
is measured from the earlier of
R/
OUT
or
OE
DATA
CE
is low during a R/
CE
W
IN
CE
Low transition occurs simultaneously with or after the R/
R/
must be High during all address transitions.
CE
W
IN
W
controlled write cycle, the write pulse width must be the larger of t
t
AS
(6)
EW
CE
t
(4)
AS
or t
or R/
(6)
CE
WP
) of
W
WP
or R/
DW
going High to the end of the write cycle.
.
CE
. If
W
t
WZ
=
) is asserted last.
OE
V
(7)
IL
t
is High during a R/
AW
and R/
W
t
t
WC
AW
W
=
t
WP (2)
V
Low transition, the outputs remain in the High-impedance state.
IL
6.02
t
.
WC
t
EW
CE CE CE CE CE
W
W W W W W
controlled write cycle, this requirement does not apply and the
(2)
t
CONTROLLED TIMING)
DW
CONTROLLED TIMING)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t
DW
WP
or (t
WZ
t
WR
+ t
(3)
DW
t
WR
) to allow the I/O drivers to turn off
t
DH
(3)
t
OW
t
DH
(1,5,8)
(1,5)
t
HZ
t
(7)
HZ
(4)
(7)
2692 drw 09
2692 drw 10
7