IDT7132 Integrated Device Technology, IDT7132 Datasheet - Page 6

• Manufacturer Part Number: IDT7132
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
NOTES:
1. Timing depends on which signal is asserted last,
2. Timing depends on which signal is deaserted first,
3. R/
4. Start of valid data depends on which timing becomes effective last t
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
NOTES:
1. Transition is measured 500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
2. 0 C to +70 C temperature range only, PLCC package only.
3. For Master/Slave combination, t
4. If
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
CAPACITANCE
NOTES:
1. This parameter is determined by device characterization but is not
2. 3dV represents the interpolated capacitance when the input and output
t
t
t
t
t
t
t
t
t
t
t
CURRENT
Symbol
Write Cycle
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Symbol
DATA
C
C
production tested.
device characterization but is not production tested.
data to be placed on the bus for the required t
write pulse can be as short as the specified t
signals switch from 0V to 3V or from 3V to 0V.
IN
OUT
OE
W
= V
is low during a R/
OUT
I
I
OE
CE
CC
SS
IH
, and the address is valid prior to or coincidental with
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Output High Z Time
Data Hold Time
Write Enabled to Output in High Z
Output Active From End of Write
Input Capacitance
Output Capacitance
Parameter
(1)
W
(T
Parameter
controlled write cycle, the write pulse width must be the larger of t
A
= +25 C,f = 1.0MHz)
(3)
(4)
WC
(1)
= t
BAA
t
Conditions
PU
+ t
V
V
IN
IN
WP
WP
DW
= 3dV
= 3dV
, since R/
(1)
.
(1)
. If
OE
50%
OE
or
OE
(2)
or
t
LZ
CE
is High during a R/
W
CE
t
Max. Unit
(1)
ACE
.
11
11
Min.
=
7132X20
.
20
15
15
15
10
—
—
0
0
0
0
V
IL
2692 tbl 10
t
CE
LZ
must occur after t
t
pF
pF
(1)
AOE
transition Low.
AOE
Max.
10
10
—
—
—
—
—
—
—
—
—
(2)
, t
6.02
(4)
ACE
7132X25
7142X25
W
,
Min. Max.
25
20
20
15
12
—
—
t
0
0
0
0
AA
controlled write cycle, this requirement does not apply and the
, and
BAA
—
—
—
—
—
—
—
10
—
10
—
t
(6)
(6)
.
BDD
MILITARY AND COMMERCIAL TEMPERATURE RANGES
.
WP
Min.
(3)
35
30
30
25
15
—
—
7132X35
7142X35
0
0
0
0
or (t
(5)
WZ
Max. Min.
VALID DATA
15
15
—
—
—
—
—
—
—
—
—
+ t
DW
) to allow the I/O drivers to turn off
55
40
40
30
20
—
—
7132X55
7142X55
0
0
0
0
t
t
PD
HZ
(4)
(2)
Max.
25
30
—
—
—
—
—
—
—
—
—
t
HZ
50%
(2)
Min. Max.
7132X100
7142X100
100
90
90
55
40
—
—
0
0
0
0
—
—
—
—
—
—
—
40
—
40
—
2692 drw 08
2692 tbl 09
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6