FW82801E Intel, FW82801E Datasheet - Page 63

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Advance Information Datasheet
Table 42. Clock Timings (Sheet 2 of 2)
Table 43. Clock Timings - UART_CLK
Table 44. PCI Interface Timing (Sheet 1 of 2)
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
Sym
Sym
t155a
t22
t23
t24
t25
t31
t32
t33
t34
t35
Sym
t10a
t12a
t40
t41
t42
t43
t44
t11a
f hl
component.
conditions.
t1a
t9a
High time
Low time
Rise time
Fall time
Operating Frequency
High time
Low time
Rise time
Fall time
CLK66 leads PCICLK
AD[31:0] Valid Delay
AD[31:0] Setup Time to PCICLK Rising
AD[31:0] Hold Time from PCICLK Rising
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PAR, PERR#, PLOCK#, DEVSEL# Valid Delay
from PCICLK Rising
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output
Enable Delay from PCICLK Rising
Operating Frequency
Frequency Tolerance
High Time
Low time
Rise Time
Fall Time
Hub Interface Clock
Parameter
Parameter
Parameter
14.7456
Min
7
7
0.25
0.25
Min
1.0
1.0
6.0
6.0
1.0
12
12
2500
Max
Min
48
3
3
2
7
0
2
2
66
Max
5.0
5.0
1.2
1.2
4.5
36
36
Max
11
11
Units
MHz
PPM
ns
ns
ns
ns
Units
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Intel
Notes
Max: 50pF
Max: 50pF
®
Min: 0pF
Min: 0pF
Notes
Notes
82801E C-ICH
3
Figure
Figure
Fig
9
9
9
9
9
9
9
9
9
9
9
9
10
11
11
10
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