FW82801E Intel, FW82801E Datasheet - Page 45

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

3.2.15
3.2.16
Advance Information Datasheet
Table 21. Other Clocks
Table 22. Universal Asynchronous Receive And Transmit (UART 0, 1) (Sheet 1 of 2)
Universal Asynchronous Receive and Transmit (UART 0,1)
Other Clocks
Signal Name
SIU0_DCD#
SIU1_DCD#
SIU0_DSR#
SIU1_DSR#
UART_CLK
SIU0_CTS#
SIU1_CTS#
SIU0_DTR#
SIU1_DTR#
(HLCLK)
CLK14
CLK48
CLK66
Name
Type
I
I
I
Type
O
I
I
I
I
Oscillator Clock: CLK14 is used for 8254 timers and runs at 14.31818 MHz.
48 MHz Clock: CLK48 is used to for the USB controller and runs at 48 MHz.
66 MHz Clock (HLCLK): CLK66 is used for the hub interface and runs at 66 MHz.
Input clock to the SIU. This clock is passed to the baud clock generation logic of
each UART in the SIU.
Clear to Send: Active low, this pin indicates that data can be exchanged
between CICH and external interface. These pins have no effect on the
transmitter.
NOTE: These pins could be used as Modem Status Inputs whose condition can
Data Carrier Detect for UART0 and UART1: Active low, this pin indicates that
data carrier has been detected by the external agent.
NOTE: These pins are Modem Status Inputs whose condition can be tested by
Data Set Ready for UART0 and UART1: Active low, this pin indicates that the
external agent is ready to communicate with 82801E C-ICH UARTs. These pins
have no effect on the transmitter.
NOTE: These pins could be used as Modem Status Input whose condition can
Data Terminal Ready for UART0 and UART1: When low these pins informs the
modem or data set that 82801E C-ICH UART0 and UART1 are ready to establish
a communication link. The DTR#x(x=0,1) output signals can be set to an active
low by programming the DTRx (x-0,1) (bit0) of the Modem control register to a
logic ‘1’. A Reset operation sets this signal to its inactive state (logic ‘1’). LOOP
mode operation holds this signal in its inactive state.
be tested by the processor by reading bit 4 (CTS) of the Modem Status
register (MSR). Bit 4 is the complement of the CTS# signal. Bit 0
(DCTS) of the MSR indicates whether the CTS# input has changed state
since the previous reading of the MSR. When the CTS bit of the MSR
changes state an interrupt is generated if the Modem Status Interrupt is
enabled.
the processor by reading bit 7 (DCD) of the Modem Status register
(MSR). Bit 7 is the complement of the DCD# signal. Bit 3 (DDCD) of the
MSR indicates whether the DCD# input has changed state since the
previous reading of the MSR. When the DCD bit of the MSR changes
state an interrupt is generated if the Modem Status Interrupt is enabled.
be tested by the processor by reading bit 5 (DSR) of the Modem Status
register. Bit 5 is the complement of the DSR# signal. Bit 1 (DDSR) of the
Modem status register (MSR) indicates whether the DSR# input has
changed state since the previous reading of the MSR. When the DSR bit
of the MSR changes state an interrupt is generated if the Modem Status
Interrupt is enabled.
Description
Description
Intel
®
82801E C-ICH
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