FW82801E Intel, FW82801E Datasheet - Page 62

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FW82801E

Manufacturer Part Number
FW82801E
Description
Communications I/O Controller Hub
Manufacturer
Intel
Datasheet

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Intel
4.4
62
Table 42. Clock Timings (Sheet 1 of 2)
®
82801E C-ICH
AC Characteristics
NOTES:
1. The USBCLK is a 48 MHz that expects a 40/60% duty cycle. The source of this PPM is external to this
2. The maximum high time (t18 Max) provide a simple guaranteed method for devices to detect bus idle
3. This specification includes pin-to-pin skew from the clock generator as well as board skew.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
f susclk
f clk48
f smb
f ioap
Sym
t10
t11
t12
t13
t14
t15
t18
t19
t20
t21
component.
conditions.
t1
t2
t3
t4
t5
t6
t7
t8
t9
Period
High Time
Low Time
Rise Time
Fall Time
Period
High Time
Low time
Operating Frequency
Frequency Tolerance
High Time
Low time
Rise Time
Fall Time
Operating Frequency
High time
Low Time
Operating Frequency
High time
Low time
Rise time
Fall time
Operating Frequency
I/O APIC Clock (APICCLK)
Suspend Clock (SUSCLK)
SMBus Clock (SMBCLK)
Oscillator Clock (OSC)
USB Clock (USBCLK)
PCI Clock (PCICLK)
Parameter
14.32
Min
4.0
4.7
30
12
12
67
20
20
48
10
10
10
7
7
32
Advance Information Datasheet
33.33
1000
Max
33.3
500
300
1.2
1.2
70
16
50
3
3
MHz
MHz
Unit
ppm
KHz
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
ns
ns
Notes
1
4
4
4
2
Figure
24
24
24
24
9
9
9
9
9
9
9
9
9
9
9
9
9
9

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