FW82801E Intel, FW82801E Datasheet - Page 40

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Intel
3.2.6
40
Table 12. IDE Interface Signals
®
82801E C-ICH
IDE Interface
/PWDMARDY#)
/SWDMARDY#)
/PRDMARDY#)
/SRDMARDY#)
/(PDSTOP)
/(SDSTOP)
/(PDWSTB
/(SDWSTB
PDD[15:0]
SDD[15:0]
PDDACK#
SDDACK#
/(PDRSTB
/(SDRSTB
PDA[2:0]
SDA[2:0]
PDDREQ
SDDREQ
PDIOW#
SDIOW#
PDCS1#
SDCS1#
PDCS3#
SDCS3#
PIORDY
SIORDY
PDIOR#
SDIOR#
Name
Type
I/O
O
O
O
O
O
O
I
I
Primary and Secondary IDE Device Chip Selects for 100 Range: These
signals are for the ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Chip Select for 300 Range: These signals
are for the ATA control register block. This output signal is connected to the
corresponding signal on the primary or secondary IDE connector.
Primary and Secondary IDE Device Address: These output signals are
connected to the corresponding signals on the primary or secondary IDE
connectors. They are used to indicate which byte in either the ATA command
block or control block is being addressed.
Primary and Secondary IDE Device Data: These signals directly drive the
corresponding signals on the primary or secondary IDE connector. There is a
weak internal pull-down resistor on PDD[7] and SDD[7].
Primary and Secondary IDE Device DMA Request: These input signals are
directly driven from the DRQ signals on the primary or secondary IDE connector.
It is asserted by the IDE device to request a data transfer, and used in
conjunction with the PCI bus master IDE function. They are not associated with
any AT-compatible DMA channel. There is a weak internal pull-down resistor on
these signals.
Primary and Secondary IDE Device DMA Acknowledge: These signals
directly drive the DAK# signals on the primary and secondary IDE connectors.
Each signal is asserted by the 82801E C-ICH to indicate to the IDE DMA slave
devices that a given data transfer cycle (assertion of DIOR# or DIOW#) is a DMA
data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function and are not associated with any AT-compatible DMA channel.
Primary and Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may drive data on the PDD or SDD lines. Data
is latched by the 82801E C-ICH on the deassertion edge of PDIOR# or SDIOR#.
The IDE device is selected either by the ATA register file chip selects (PDCS1# or
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the IDE DMA
acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is
the data write strobe for writes to disk. When writing to disk, 82801E C-ICH drives
valid data on rising and falling edges of PDWSTB or SDWSTB.
Primary and Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This
is the DMA ready for reads from disk. When reading from disk, 82801E C-ICH
deasserts PRDMARDY# or SRDMARDY# to pause burst data transfers.
Primary and Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the
command to the IDE device that it may latch data from the PDD or SDD lines.
Data is latched by the IDE device on the deassertion edge of PDIOW# or
SDIOW#. The IDE device is selected either by the ATA register file chip selects
(PDCS1# or SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): 82801E C-ICH asserts this
signal (PDSTOP, SDSTOP) to terminate a burst.
Primary and Secondary I/O Channel Ready (PIO): This signal keeps the strobe
active (PDIOR# or SDIOR# on reads, PDIOW# or SDIOW# on writes) longer than
the minimum width. It adds wait states to PIO transfers.
Primary and Secondary Disk Read Strobe (Ultra DMA Reads from Disk):
When reading from disk, 82801E C-ICH latches data on rising and falling edges
of this signal from the disk.
Primary and Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When
writing to disk, this is deasserted by the disk to pause burst data transfers.
Description
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