FW82801E Intel, FW82801E Datasheet - Page 11

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

2.0
2.1
Advance Information Datasheet
Figure 3. Ball Diagram (Top View)
AA
AB
AC
W
M
G
A
B
C
D
E
H
K
N
P
R
U
V
Y
F
T
J
L
MANAGEMENT
SMBALERT#/
FRAME# AD[16]
C/BE[1]# AD[14]
PCIRST#
GPIO[11]
USBP1P
NC[10]
SERR#
GPIO[8]
AD[13]
AD[23]
AD[27]
AD[29]
V5REF TP[3]
AD[0]
AD[7]
OC0#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
1
POWER
Package Information
Ball Location
This section describes the 82801E C-ICH ball assignment. Figure 3 provides a 421-ball location
diagram. The diagram also indicates general signal groupings. Table 4 lists the 82801E C-ICH
signal assignments by ball number. Table 5 lists the assignments alphabetically by signal name.
GPIO[12]
GPIO[25]
SMBCLK
C/BE[2]#
GPIO[7]
USBP1N
Vcc1_8
AD[19]
AD[31]
NC[11]
NC[8]
AD[28]
AD[20]
AD[10]
AD[12]
AD[25]
AD[4]
NC[9]
TP[2]
VSS
2
2
RSM_PWROK
DEVSEL#
GPIO[27]
GPIO[13]
GNT[3]#
GPIO[6]
SUSCLK
Vcc3_3
AD[22]
AD[15]
AD[17]
Vcc3_3
Vcc3_3
AD[9]
AD[6]
AD[8]
NC[7]
V5REF
PAR
VSS
VSS
VSS
VSS
3
3
RESERVED2
RESERVED1
SMLINK[1]
C/BE[0]#
C/BE[3]#
SMBDATA
GPIO[24]
GPIO[28]
USBP0P
REQ[3]#
STOP#
TRDY#
PERR#
NC[12]
OC[1]#
AD[26]
IRDY#
NC[4]
AD[3]
AD[1]
VSS
NC[6]
VSS
4
4
INTRUDER#
SMLINK[0] VSS
PIRQ[A]# VSS
USBP0N
REQ[0]# NC[5]
PLOCK# Vcc3_3
PCICLK
Vcc1_8
V5REF Vcc3_3
AD[30]
AD[18] AD[24]
AD[11] Vcc3_3
AD[2]
AD[5]
AD[21]
TP[1]
VSS
VSS
VSS
VSS
VSS
VSS
RI#
5
5
RTCRST#
Vcc3_3
Vcc3_3
Vcc3_3
VBIAS
PCI
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
VSS
VSS
VSS
6
6
PIRQ[H]#/
RTCX1
PIRQ[D]#
PIRQ[C]#
REQ[1]#
GPIO[5]
Vcc3_3
Vcc3_3
RTCX2
NC[1]
NC[3]
VSS
VSS
7
7
SMLINK
RSMRST#
VccRTC
PIRQ[E]#
PIRQ[B]#
GNT[0]#
VCC1_8
GNT[2]#
VccRTC
Vcc1_8
Vcc3_3
CLK48
VSS
8
8
APICCLK
GNT[B]#/
GNT[5]#/
GPIO[17]
REQ[A]#/
REQ[2]#
PWROK
APICD[0]
GPIO[0]
Vcc3_3
FERR#
Vcc1_8
NC[2]
VSS
VSS
9
9
GPIO[21]
REQ[B]#/
PIRQ[F]#
APICD[1]
REQ[5]#/
GNT[A]#/
GPIO[16]
GPIO[1]
GNT[1]#
SERIRQ
Vcc1_8
Vcc1_8
Vcc1_8
Vcc1_8
Vcc3_3
Vcc3_3
V5REF
SPKR
10
10
VSS
VSS
PIRQ[G]#/
LDRQ[0]#
LDRQ[1]#
GPIO[4]
THRM#
PDD[6]
PDD[7]
PDD[8] PDD[4]
V5REF
CLK14 PDD[5]
PDD[9]
11
11
VSS
VSS
VSS
VSS
VSS
PDD[10]
PDD[11]
LAD[0]/
FWH[0]
LAD[1]/
FWH[1]
LAD[2]/
FWH[2]
Vcc1_8
Vcc1_8
VSS LFRAME#/
12
TP[0]
12
VSS
VSS
VSS
VSS
LPC
FWH[4]
RESET#
PDD[12]
LAD[3]/
FWH[3]
PDD[1]
PDD[3]
PDD[13]
LCLK
SIU_
SIU_
VSS
VSS
13
VSS
VSS
VSS
VSS
VSS
13
PDCS1#
PDIOW#
PDD[0]
PDD[14]
Vcc1_8
Vcc1_8
Vcc1_8
Vcc3_3
PDD[2]
LAD[0]
LAD[3]
SIU_
SERIRQ
LAD[2]
Vcc1_8
Vcc1_8
Vcc1_8
SIU_
SIU_
SIU_
VSS
14
14
LFRAME#
PDDACK#
PDDREQ
PDD[15]
Vcc3_3
Vcc3_3
PDA[1]
SDD[6]
SIU1_
SIU_
LAD[1]
SIU_
LDRQ#
VSS
15
15
RI#
SIU_
IRQ[14]
Vcc3_3
SDD[5]
PDA[0]
PDA[2]
SIU1_
SIU1_
SIU1_
Vcc3_3
RTS#
DTR#
CTS#
SIU0_
16
SIU1_
DCD#
RTS#
VSS
16
IDE
VCC3_3
SDD[14]
SDD[10]
PIORDY
PDIOR#
Vcc3_3
Vcc3_3
SDD[8]
SIU0_
CTS#
SIU0_
RXD
17
VSS
17
SIU1_
TXD
SIU
Vcc3_3
Vcc3_3
Vcc1_8
SDD[12]
SDD[9]
Vcc3_3
SDIOR#
Vcc3_3
Vcc3_3
Vcc3_3
Vcc1_8
Vcc1_8
Vcc1_8
Vcc1_8
Vcc3_3
SDD[4]
SDD[7]
18
SIU1_
DSR#
SIU1_
SIU0_
DSR#
18
RXD
CPUSLP#
SDDACK#
HLCOMP
SDCS1#
GPIO[20]
SDIOW#
EE1_CS
SDD[11]
PDCS3#
UART_
SDD[0]
SDD[3]
SIU0_
SIU0_
DTR#
HL[0]
HL[9]
HL[4]
RXD[1]
CLK
VSS
TXD
VSS
LAN1_
HL[7]
19
19
EE1_
DIN
VSS
GPIO[23]
EE0_CS
HUBREF
SIORDY
GPIO[22]
SDD[15]
SDD[13]
SHCLK
RXD[0]
SDD[2]
LAN1_
TXD[0]
LAN1_
TXD[2]
LAN0_
SDA[2]
SIU0_
DCD#
DOUT
EE1_
EE0_
HL[3]
HL[5]
VSS
VSS
VSS
VSS
20
VSS
20
VSS
VRMPWRGD
V_CPU_IO
Intel
SDCS3#
LAN1_
LAN1_
RXD[0]
SDA[1]
Vcc1_8
Vcc3_3
LAN0_
TXD[1]
LAN0_
TXD[0]
SDD[1]
21
SIU0_
DOUT
HL[10]
21
CLK
EE1_
EE0_
HL[1]
SMI#
VSS
VSS
VSS
VSS
VSS
INIT#
RI#
DIN
CPUPWRGD
LAN0_CLK
RSTSYNC
V_CPU_IO
STPCLK#
GPIO[18]
SDDREQ
HL_STB
Vcc1_8
RXD[2]
Vcc1_8
IRQ[15]
LAN1_
TXD[1]
LAN1_
LAN0_
HL[11]
VSS
22
HL[8]
22
®
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NMI
82801E C-ICH
RSTSYNC
(HLCLK)
IGNNE#
A20GATE
HL_STB#
GPIO[19]
Vcc1_8
LAN0_
RXD[1]
CLK66
RCIN#
LAN0_
LAN0_
TXD[2]
A20M#
SDA[0]
SHCLK
23
VSS
LAN1_
RXD[2]
VSS
23
HL[2]
HL[6]
INTR
EE0_
VSS
VSS
VSS
VSS
A8684-02
AA
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
11