S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 80

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

80
VCC and VIO Power-up And Power-
down Sequencing
Standby Mode
Figure: Test Setup
Table: Alternate CE# Controlled Erase/
Program Operations
Table: Memory Array Command
Definitions (x32 Mode)
Revision B4 (October 30, 2009)
Absolute Maximum Ratings
DC Characteristics
Synchronous Operation
Hardware Reset (RESET#)
Revision B5 (May 25, 2011)
Physical Dimensions/Connection
Diagrams
Revision B6 (March 15, 2012)
Global
Additional Resources
Revision History
Revision B7 (October 11, 2012)
Valid Combinations
Asynchronous Operations
Erase/Program Operations
Section
Added reference to timing section.
Changed Vcc ± 0.2V to Vcc ± 10%.
Removed Note “Diodes are IN3064 or equivalent”.
Corrected values for t
Cleaned up Notes.
Corrected Address, Data, Control Signals identifiers to correctly distinguish different ratings
between CL016L, CL032J, CD016J, and CD032J.
Added line item to distinguish V
Corrected Figure “Burst Mode Read (x32 Mode)” to reflect max linear burst length of 8 double words
instead of 32.
Corrected Table “Burst Initial Access Delay”: changed t
instead of Max.
Corrected Figure “RESET# Timings” to add t
embedded algorithm.
On the 80-ball Fortified BGA Connection Diagram, corrected the K1 pin name from V
Added LAD080 Fortified BGA package option and drawing.
Updated relevant application note links.
Corrected heading for May 25, 2011 edits from revision B4 to B5.
Updated Valid Combinations table to add clarity and make explicit which offerings require a
customer to “contact factory for availability”.
In Figure 18.3, “Asynchronous Command Write Timing”, corrected the t
the Stable Address period, not the Valid Data period.
In Table 18.5, “Erase/Program Operations”, corrected JEDEC symbol t
In Table 18.5, merged redundant rows t
In Figures 18.8 “Program Operation Timings” and 18.9 “Chip/Sector Erase Operation Timings”,
corrected t
S29CD-J and S29CL-J Flash Family
AH
measurement to be from the falling edge of WE#.
DH
with separate values for 16 Mb and 32 Mb.
D a t a
IHCLK
value differences between CL-J and CD-J.
GHWL
S h e e t
Description
READY2
and t
WEH
to timing diagram for bank not executing
READY2
.
S29CD-J_CL-J_00_B7 October 11, 2012
, t
RP
, and t
AVAV
WC
READY3
measurement to be of
to t
AVAX
set up to Min
.
CCQ
to V
IO
.