S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 10

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

2. Input/Output Descriptions and Logic Symbols
10
Table identifies the input and output package connections provided on the device.
DQ31-DQ0
RESET#
Symbol
RY/BY#
A19-A0
WAIT#
ADV#
IND#
WE#
WP#
OE#
ACC
CE#
CLK
V
V
V
NC
CC
SS
IO
No Connect
Supply
Supply
Supply
Output
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
S29CD-J and S29CL-J Flash Family
Address lines for S29CD-J and S29CL-J (A18-A0 for 16 Mb and A19-A0 for 32 Mb).
A9 supports 12V autoselect input.
Data input/output
Chip Enable. This signal is asynchronous relative to CLK for the burst mode.
Output Enable. This signal is asynchronous relative to CLK for the burst mode.
Write Enable
Device Power Supply. This signal is asynchronous relative to CLK for the burst mode.
VersatileI/O
Ground
Not connected internally
Ready/Busy output and open drain which require a external pull up resistor.
When RY/BY# = V
When RY/BY# = V
device is executing a hardware reset operation.
Clock Input that can be tied to the system or microprocessor clock and provides the
fundamental timing and internal operating frequency.
Load Burst Address input. Indicates that the valid address is present on the address
inputs.
End of burst indicator for finite bursts only. IND is low when the last word in the burst
sequence is at the data outputs.
Provides data valid feedback only when the burst length is set to continuous.
Write Protect Input. At V
sectors of the large bank.
Acceleration input. At V
acceleration, ACC = V
Hardware Reset.
TM
D a t a
Input.
OH
OL
, the device is either executing an embedded algorithm or the
, the device is ready to accept read operations and commands.
SS
HH
IL
S h e e t
or V
, disables program and erase functions in two outermost
, accelerates erasing and programming. When not used for
CC
.
Description
S29CD-J_CL-J_00_B7 October 11, 2012