S29CD-J_12 SPANSION [SPANSION], S29CD-J_12 Datasheet - Page 28

• Manufacturer Part Number: S29CD-J_12
• Manufacturer: SPANSION [SPANSION]

28
8.4.2
Initial Burst Access Delay
Note
Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address, 4-doubleword burst,
output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-around.
Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge when the data is valid.
Burst access is initiated and the address is latched on the first rising CLK edge when ADV# is active or upon
a rising ADV# edge, whichever comes first. The Initial Burst Access Delay is determined in the Configuration
Register (CR13-CR10). Refer to
Figure 8.4
access has no effect on asynchronous read operations.
IND/WAIT#
Addresses
(DOC)
CR13
CR9
0
0
0
0
0
0
0
0
0
Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 4 Double Word Burst Operation
ADV#
Data
OE#
CE#
CLK
for the Initial Burst Delay Control timing diagram. Note that the Initial Access Delay for a burst
V
V
(WC)
CR8
IH
IL
CR12
0
1
Address 1
0
0
0
1
1
1
1
Table 8.3 Valid Configuration Register Bit Definition for IND/WAIT#
(CC)
CR6
1
1
CR11
S29CD-J and S29CL-J Flash Family
0
1
1
0
0
1
1
Address 1 Latched
3 Clock Delay
IND/WAIT# = V
IND/WAIT# = V
CLK edge
Table 8.5
Table 8.4 Burst Initial Access Delay
Address 2
CR10
1
0
1
0
1
0
1
for the initial access delay configurations under CR13-CR10. See
D a t a
IL
IL
for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
for 1-CLK cycle, Active on second to last transfer, Driven on rising
Invalid
S h e e t
Initial Burst Access (CLK cycles)
Definition
D1
S29CD-J_CL-J_00_B7 October 11, 2012
3
4
5
6
7
8
9
D2
D3
D0