AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 8

• Manufacturer Part Number: AD5415YRU-REEL
• Description: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
• Manufacturer: AD [Analog Devices]

AD5415
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4–7
8
9
10
11
12
13
14
15
16
17
18–21
22
23
24
Mnemonic
I
I
R
R1A–R3A
V
GND
LDAC
SCLK
SDIN
SDO
SYNC
CLR
V
V
R1B–R3B
R
I
I
OUT
OUT
OUT
OUT
FB
FB
REF
DD
REF
A
B
1A
2A
2B
1B
A
B
DAC A Current Output.
DAC A Reference Voltage Input Pin.
Ground Pin.
Function
DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge
when the device is in standalone mode or on the rising edge of SYNC when in daisy-chain mode.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
Active Low Control Input. The frame synchronization signal for the input data. When SYNC goes low, it powers on
the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift
register on the 16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear to zero scale or midscale, as required.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum of external components.
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC B Current Output.
I
I
R2_3A
OUT
OUT
V
LDAC
SCLK
R
REF
SDIN
GND
R3A
R1A
R2A
FB
1A
2A
Figure 5. Pin Configuration
A
A
12
10
11
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1
2
3
4
5
6
7
8
9
(Not to Scale)
TOP VIEW
AD5415
24
23
22
21
20
19
18
17
16
15
14
13
I
I
R
R1B
R2B
R2_3B
R3B
V
V
CLR
SYNC
SDO
OUT
OUT
REF
DD
FB
B
1B
2B
B