AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 16

• Manufacturer Part Number: AD5415YRU-REEL
• Description: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
• Manufacturer: AD [Analog Devices]

AD5415
BIPOLAR OPERATION
In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and the on chip 4-quadrant resistors, as shown in
Figure 34.
When in bipolar mode, the output voltage is given by
where D is the fractional representation of the digital word
loaded to the DAC, in the range of 0 to 4095.
n is the number of bits.
When V
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
V
OUT
IN
= V
is an ac signal, the circuit performs 4-quadrant
REF
× D/2
n − 1
−V
AGND
REF
V
IN
Analog Output (V)
+V
0
−V
V
A1
REF
REF
REF
(2048/2048)
(2047/2048)
(2047/2048)
R2_3A
R2A
R3A
NOTES:
1
2
DAC B OMITTED FOR CLARITY.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
V
V
DD
REF
R3
2R
R2
2R
R1A
A
SYNC
Figure 34. Bipolar Operation
R1
2R
uCONTROLLER
12-BIT DAC A
Rev. 0 | Page 16 of 28
AD5415
SCLK
R
R
2R
FB
SDIN
STABILITY
In the I-to-V configuration, the I
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response that can cause ringing or instability in the closed loop
application’s circuit.
An optional compensation capacitor, C1, can be added in
parallel with R
Figure 34. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
AGND
GND
I
I
OUT
OUT
R
FB
1A
2A
A
AGND
C1
FB
A1
for stability, as shown in Figure 33 and
V
OUT
= –V
IN
TO +V
OUT
IN
of the DAC and the