AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 20

• Manufacturer Part Number: AD5415YRU-REEL
• Description: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
• Manufacturer: AD [Analog Devices]

AD5415
SERIAL INTERFACE
The AD5415 has an easy-to-use 3-wire interface, which is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. Data is written to the device in 16-bit words. Each
16-bit word consists of four control bits and 12 data bits, as
shown in Figure 39.
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC . The SCLK and DIN input buffers
are powered down on the rising edge of SYNC .
DAC Control Bits C3 to C0
Control bits C3 to C0 allow control of various functions of the
DAC, as shown in Table 11. Default settings of the DAC at
power-on are as follows. Data is clocked into the shift register
on falling clock edges; daisy-chain mode is enabled. The device
powers on with zero-scale load to the DAC register and I
lines. The DAC control bits allow the user to adjust certain
features at power-on. For example, daisy-chaining can be
disabled when not in use, active clock edge can be changed to
rising edge, and DAC output can be cleared to either zero scale
or midscale. The user can also initiate a readback of the DAC
register contents for verification purposes.
CONTROL REGISTER
(Control Bits = 1101)
While maintaining software compatibility with the single-
channel current output DACs (AD5426/AD5433/AD5443), this
DAC also features some additional interface functionality.
Simply set the control bits to 1101 to enter control register
mode. Figure 40 shows the contents of the control register, the
functions of which are described in the following sections.
DB15 (MSB)
DB15 (MSB)
C3
1
CONTROL BITS
CONTROL BITS
C2
1
C1
0
C0
1
SDO1 SDO2
DB11 DB10
Figure 39. AD5415 12-Bit Input Shift Register Contents
Figure 40. Control Register Loading Sequence
OUT
DB9
DSY HCLR SCLK
Rev. 0 | Page 20 of 28
DB8
DB7
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-
drain driver. The strength of the SDO driver affects the timing
of t
Table 10. SDO Control Bits
SDO2
0
0
1
1
Daisy-Chain Control (DSY)
DSY enables or disables daisy-chain mode. A 1 enables daisy-
chain mode; a 0 disables it. When disabled, a readback request is
accepted, SDO is automatically enabled, the DAC register
contents of the relevant DAC are clocked out on SDO, and,
when complete, SDO is disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR pin is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
clears the DAC outputs to midscale; a 0 clears them to
zero scale.
Active Clock Edge (SCLK)
The default active clock edge is the falling edge. Write a 1 to this
bit to clock data in on the rising edge; write a 0 to clock it on the
falling edge.
DB6
DATA BITS
X
12
and, when stronger, allows a faster clock cycle to be used.
DB5
X
SDO1
0
1
0
1
DB4
X
DB3
Function
Full SDO Driver
SDO Configured as Open Drain
Weak SDO Driver
Disable SDO Output
X
DB2
X
DB1
X
DB0 (LSB)
DB0 (LSB)
DB0
X