AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 22

• Manufacturer Part Number: AD5415YRU-REEL
• Description: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
• Manufacturer: AD [Analog Devices]

AD5415
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5415 DAC is through a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communications channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5415 requires a 16-bit word,
with the default being data valid on the falling edge of SCLK,
but this is changeable using the control bits in the data-word.
ADSP-21xx to AD5415 Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5415 DAC without the need for extra glue logic. Figure 40
is an example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL.
A serial interface between the DAC and DSP SPORT is shown
in Figure 42. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface
expects a t
of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame sync frequencies for the
SPORT register.
Table 12 shows the set up for the SPORT control register.
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to AD5415 Interface
ADSP-2101/
ADSP-2103/
ADSP-2191*
ADSP-2191*
4
(SYNC falling edge to SCLK falling edge setup time)
SPIxSEL
Figure 41. ADSP-2191 SPI to AD5415 Interface
SCLK
MOSI
SCK
TFS
DT
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5415*
AD5415*
Rev. 0 | Page 22 of 28
Table 12. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
80C51/80L51 to AD5415 Interface
A serial interface between the DAC and the 80C51 is shown in
Figure 43. TXD of the 80C51 drives SCLK of the DAC serial
interface, while RXD drives the serial data line, DIN. P3.3 is a
bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
therefore, only eight falling clock edges occur in the transmit
cycle. To load data correctly to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. Data on RXD is
clocked out of the microcontroller on the rising edge of TXD
and is valid on the falling edge. As a result, no glue logic is
required between the DAC and microcontroller interface. P3.3
is taken high following the completion of this cycle. The 80C51
provides the LSB of its SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
into account.
MC68HC11 Interface to AD5415 Interface
Figure 44 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, Clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface, the MOSI
output drives the serial data line (DIN) of the AD5516.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5516, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
*ADDITIONAL PINS OMITTED FOR CLARITY
8051*
1
1
Figure 43. 80C51/80L51 to AD5415 Interface
Setting
1
1
1
1111
00
P1.1
RxD
TxD
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
SCLK
SDIN
SYNC
AD5415*