AD5415YRU-REEL AD [Analog Devices], AD5415YRU-REEL Datasheet - Page 6

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AD5415YRU-REEL

Manufacturer Part Number
AD5415YRU-REEL
Description
Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface
Manufacturer
AD [Analog Devices]
Datasheet
AD5415
SYNC
SCLK
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
t
4
DB15
(N)
t
5
t
6
TO OUTPUT
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
Figure 4. Load Circuit for SDO Timing Specifications
PIN
t
2
50pF
C
L
200µA
200µA
t
1
Rev. 0 | Page 6 of 28
t
3
t
12
DB0
(N)
I
I
OL
OH
DB15
(N+1)
DB15
(N)
V
OH
(MIN) + V
2
OL
(MAX)
(N+1)
DB0
DB0
(N)
t
7
t
8

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