mk68901 STMicroelectronics, mk68901 Datasheet - Page 9
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mk68901
Manufacturer Part Number
mk68901
Description
Multi.function Peripheral
Manufacturer
STMicroelectronics
Datasheet
1.MK68901.pdf
(33 pages)
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Figure 11 b : Daisy Chaining.
Each interrupt channel responds with a discrete 8-
bit vector when acknowledged. The upper four bits
of the vector are set by writing the upper four bits of
the VR. The four low order bits (bit 3-bit 0) are ge-
nerated by the interrupting channel.
To acknowledge an interrupt, IACK goes low, the IEI
input must go low (or be tied low) and the MK68901
MFP must have an acknowledgeable interrupt pen-
ding. The Daisy Chaining capability (figure 11) re-
quires that all parts in a chain have a common IACK.
When the common IACK goes low, all parts freeze
and prioritize interrupts in parallel. Then priority is
passed down the chain, via IEI and IEO, until a part
which has a pending interrupt is reached. The part
with the pending interrupt, passes a vector, does not
propagate IEO, and generates DTACK.
Figure 9 describes the 16 prioritized interrupt chan-
nels. As chown, General Purpose Interrupt 7 has the
highest priority, while General Purpose Interrupt 0 is
assigned the lowest priority. Each of these channels
may be reprioritized, in effect, by selectively ma-
sking interrupts under software control. The binary
numbers under ”channel” correspond to the modi-
fied bits IV3, IV2, IV1 and IV0, respectively, of the
Interrupt Vector for each channel (see figure 6).
Each channel has an enable bit contained in IERA
or IERB, a pending latch contained in IPRA or IPRB,
a mask bit contained in IMRA or IMRB, and an in–
service latch contained in ISRA or ISRB. Additional-
ly, the eight General Purpose Interrupts each have
an edge bit contained in the Active Edge Register
(AER), a bit to define the line as input or output
contained in the Data Direction Register (DDR) and
an I/O bit in the General Purpose Interrupt-I/O Port
(GPIP).
TIMERS
There are four timers on the MK68901 MFP. Two of
the timers (Timer A and Timer B) are full function ti-
mers which can perform the basic delay function
and can also perform event counting, pulse width
measurement, and waveform generation. The other
two timers (Timer C and Timer D) are delay timers
only. One or both of these timers canbe used to sup-
ply the baud rate clocks for the USART. All timers
are prescaler/counter timers with a common inde-
pendent clock input (XTAL1, XTAL2). In addition, all
timers have a time-out output, function that toggles
each time the timer times out.
The four timers are programmed via three Timer
Control Registers and four Timer Data Registers. Ti-
mers A and B are controlled by the control registers
TACR and TBCR, respectively (see figure 12), and
by the data registers TADR and TBDR (figure 13).
Timers C and D are controlled by the control register
TCDCR (see figure 14) and two data registers
TCDR and TDDR. Bits in the control registers allow
the selection of operational mode, prescale, and
control white the data registers are used to read the
timer or write into the time constant register. Timer
A and B input pins TAI and TBI, are used for the e-
vent and pulse width modes for timers A and B.
With the timer stopped, no counting can occur. The
timer contents will remain unaltered while the timer
is stopped (unless reloaded by writing the Timer Da-
ta Register), but any residual count in the prescaler
will be lost.
MK68901
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