mk68901 STMicroelectronics, mk68901 Datasheet - Page 16

• Manufacturer Part Number: mk68901
• Description: Multi.function Peripheral
• Manufacturer: STMicroelectronics

MK68901
There are two interrupt channels associated with the
receiver. One channel is used for the normal Buffer
Full condition, while the other channel is used whe-
never an error condition occurs. Only one interrupt
is generated per word received, but dedicating two
channels allows separate vectors : one for the nor-
mal condition, and one for an error condition. If the
error channel is disabled, an interrupt will be gen-e-
rated via the Butter Full Channel, whether the word
received is normal or in error. Those conditions
which produce an interrupt via the error channel
are : Overrun, Parity Error, Frame Error, Sync
Found, and Break. If a received word has an error
associated with it, and the error interrupt channel is
enabled, an interrupt will occur on the error channel
only.
Each time a word is transferred into the receive buf-
fer, a corresponding set of flags is latched into the
RSR. No flags (except CIP) are allowed to change
until the data word has been read from the receive
buffer. Reading the receive buffer allows a new data
word to be transferred to the receive buffer when it
is received. Thus one should first read the RSR then
read the receive buffer (UDR) to ensure that the
flags just read match the data word just read. If done
in the reverse order, it is possible that subsequent
to reading the data word from the receive buffer, but
prior to reading the RSR, a new word may be recei-
ved and transferred to the receive buffer and, with
it, its associated flags latched into the RSR. Thus,
when the RSR is read, those flags may actually cor-
respond to a different data word. It is good practice,
also to read the RSR prior to a data read as, when
an overrun error occurs, the receiver will not assem-
ble new characters until the RSR has been read.
As previously stated, when overrun occurs, the OE
flag will not be set and the associated interrupt will
not be generated until the receive buffer has been
read. If a break occurs, and the receive buffer has
not yet been read, only the B flag will be set (OE will
Figure 19 : Transmitter Status Register (TSR).
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not be set). Again, this flag will not be set until the
last valid word has been read from the receive buf-
fer. If the break condition ends and another whole
data word is received before the receive buffer is
read, both the B and OE flags will be set once the
receive buffer is read.
If a break occurs while the OE flag is set, the B flag
will also be set.
A break generates an interrupt when the condition
occurs and again when the condition ends. If the
break condition ends before it is acknowledged by
reading the RSR, the receiver error interrupt indica-
ting end of break will be generated once the RSR is
read.
Anytime the asynchronous format is selected, start
bit detection is enabled. New data is not shifted into
the shift register until a zero bit is detected. If a 16
clock is selected, along with the asynchronous for-
mat, false start bit detection is also enabled. Any
transition has to be stable for 3 positive going edges
of the receive clock to be called a valid transition. For
a start bit to be good, a valid 0-1 transition must not
occur for 8 positive clock transitions after the initial
valid 1-0 transition.
After a good start bit has been detected, valid tran-
sitions in the data are checked for continously.
When a valid transition is detected, the counter is
forced to state zero, andno more transition checking
is started until state four. At state eight, the ”previous
state” of the transition checking logic is clocked into
the receiver.
As a result of this resynchronization logic, it is pos-
sible to run with asynchronous clocks without start
and stop bits if there are sufficient valid transitions
in the data stream. This logic also makes the unit
more tolerant of clock skew for normal asynchro-
nous communications than a device which employs
only start bit synchronization.
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