mk68901 STMicroelectronics, mk68901 Datasheet - Page 4
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mk68901
Manufacturer Part Number
mk68901
Description
Multi.function Peripheral
Manufacturer
STMicroelectronics
Datasheet
1.MK68901.pdf
(33 pages)
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MK68901
Figure 4 : Register Map.
INTERRUPTS
The General Purpose I/O-Interrupt Port (GPIP) pro-
vides eight I/O lines that may be operated either as
inputs or outputs under software control. In addition,
each line may generate an interrupt in either a po-
sitive going edge or a negative going edge of the in-
put signal.
The GPIP has three associated registers. One al-
lows the programmer to specify the Active Edge for
each bit that will trigger an interrupt. Another register
specifies the Data Direction (input or output) asso-
ciated with each bit. The third register is the actual
data I/O register used to input or output data to the
port. These three registers are illstrated in figure 5.
The Active Edge Register (AER) allows each of the
General Purpose Interrupts to provide an interrupt
on either a 1-0 transition or a 0-1 transition. Writing
a zero to the appropriate bit of the AER causes the
associated input to produce an interrupt on the 1-0
transition. The edge bit is simply one input to an ex-
clusive-or gate, with the other input coming from the
input buffer ant the output going to a 1-0 transition
detector. Thus, depending upon the state of the in-
put, writing the AER can cause an interrupt-produ-
cing transition, which will cause an interrupt on the
associated channel, if that channel is enabled. One
4/33
Address Port N .
10
11
12
13
14
15
16
17
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
Abbreviation
TCDCR
TCDR
TDDR
TACR
TBCR
TADR
TBDR
IMRA
IMRB
GPIP
IERA
IERB
IPRA
IPRB
ISRA
ISRB
DDR
SCR
UCR
RSR
UDR
AER
TSR
VR
Register N ame
GENERAL PURPOSE I/O
ACTIVE EDGE REGISTER
DATA DIRECTION REGISTER
INTERRUPT ENABLE REGISTER A
INTERRUPT ENABLE REGISTER B
INTERRUPT PENDING REGISTER A
INTERRUPT PENDING REGISTER B
INTERRUPT IN-SERVICE REGISTER A
INTERRUPT IN-SERVICE REGISTER B
INTERRUPT MASK REGISTER A
INTERRUPT MASK REGISTER B
VECTOR REGISTER
TIMER A CONTROL REGISTER
TIMER B CONTROL REGISTER
TIMERS C AND D CONTROL REGISTER
TIMER A DATA REGISTER
TIMER B DATA REGISTER
TIMER C DATA REGISTER
TIMER D DATA REGISTER
SYNC CHARACTER REGISTER
USART CONTROL REGISTER
RECEIVER STATUS REGISTER
TRANSMITTER STATUS REGISTER
USART DATA REGISTER
would then normally configure the AER before
enabling interrupts via IERA and IERB.
Note : Changing the edge bit, with the interrupt
enabled, may cause an interrupt on that channel.
The Data Direction Register (DDR) is used to define
10-17 as inputs or as outputs on a bit by bit basis.
Writing a zero into a bit of the DDR causes the cor-
responding Interrupt-I/O pin to be a Hi-Z input. Wri-
ting a one into a bit of the DDR causes the cor-
responding pin to be configured as a push-pull out-
put. When data is written into the GPIP, those pins
defined as inputs will remain in the Hi-Z state while
those pins defined as outputs will assume the state
(high or low) of their corresponding bit in the GPIP.
When the GPIP is read, the data read will come di-
rectly from the corresponding bit of the GPIPregister
for all pins defined as output, while the data read on
all pins defined as inputs will come from the input
buffers.
Each individual function in the MK68901 is provided
with a unique interrupt vector that is presented to the
system during the interrupt acknowledge cycle. The
interrupt vector returned during the interrupt ac-
knowledge cycle is shown in figure 6, while the vec-
tor register is shown in figure 7.