mk68901 STMicroelectronics, mk68901 Datasheet - Page 19

• Manufacturer Part Number: mk68901
• Description: Multi.function Peripheral
• Manufacturer: STMicroelectronics

Unused bits in the sync character register are ze-
roed out ; therefore, word length should be set up
prior to writing the sync word in some cases. Sync
word length is the word length plus one when parity
is enabled. The user has to determine the parity of
the sync word when the word length is not 8 bits. The
MK68901 MFP does not add a parity bit to the sync
word if the word length is less than 8 bits. The extra
bit in the sync word is transmitted as the parity bit.
With a word length of eight, and parity selected, the
parity bit for the sync word is computed an added on
by the MK68901 MFP.
RR RECEIVER READY
RR is asserted when the Buffer Full bit is set in the
RSR unless a parity error or frame error is detected
by the receiver.
TR TRANSMITTER READY
TR is asserted when the Buffer Empty bit is set in the
TSR unless a break is currently being transmitted.
REGISTER ACCESSES
All register accesses are dependent on CLK as
shown in the timing diagrams. To read a register, CS
and DS must be asserted, and R/W must by high. The
internal read control signal is essentially the combi-
nation of CS, DS, and RD/WR. Thus, the read ope-
ration will begi n when CS and DS go active and will
end when either CS or DS goes inactive. The address
bus must be stable prior to the start of the operation
and must remain stable until the end of the operation.
Unless a read operation or interrupt acknowledge cy-
cle is in progress the data bus (D
the tri-state condition.
To write a register, CS and DS must be asserted and
R/W must be low. The address must be stable prior
to the start of the operation and must remain stable
until the end of the operation. After the MK68901 as-
serts DTACK, the CPU negates DS,. At this time, the
MFP latches the data bus and writes the contents in-
to the appropriate register. Also when DS is nega-
ted, the MFP rescinds DTACK.
For an interrupt acknowledge, the operation starts
when IACK goes low, and ends when IACK goes
high. The data bus is tri-stated when either IACK or
DS goes high.
When CS or IACK are asserted the MFP starts an
internal cycle. DS is needed to enable the address
and data buffers. It is recommended taht CS and
IACK be gated by DS so that DS is always present
whenever an MFP bus cycle starts.
0
-D
7
) will remain in
MK68901
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