mk68901 STMicroelectronics, mk68901 Datasheet - Page 22

• Manufacturer Part Number: mk68901
• Description: Multi.function Peripheral
• Manufacturer: STMicroelectronics

MK68901
Notes :
22/33
AC ELECTRICAL CHARACTERISTICS (continued)
(V
Number
C C
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
= 5.0Vdc
1. IEO only goes low if no acknowledgeable interrupt is
2. T
3. If the setup time is not met, CS or IACK will not be reco-
4. If this setup time is met (for consecutive cycles), the mi-
pending. If IEO goes low, DTACK and the data bus re-
main tri-stated.
pin. t
whether that signal comes from the XTAL 1/XTAL2crys-
tal clock inputs or the TAI or TBI timer inputs.
gnized until the next falling CLK.
nimum hold-off time of one clock cycle will be obtained.
If not met, the hold-off will be two clock cycles.
Timer Clock High Time
Timer Clock Cycle Time
RESET Low Time
Delay to Falling INTR from External Interrupt
Active Transition
Transmitter Internal Interrupt Delay from Falling
Edge of TC
Receiver Buffer Full Interrupt Transition Delay
from Rising Edge of RC
Receiver Error Interrupt Transition Delay from
Falling Edge of RC
Serial in Set Up Time to Rising Edge of RC
(divide by one only)
Data Hold Time from Rising Edge of RC
(divide by one only)
Serial Output Data Valid from Falling Edge of TC
( 1)
Transmitter Clock Low Time
Transmitter Clock High Time
Transmitter Clock Cycle Time
Receiver Clock Low Time
Receiver Clock High Time
Receiver Clock Cycle Time
CS, IACK, DS Width Low
Serial Output Data Valid from Falling Edge of TC
( 16)
CLK
CLK
refers to the clock applied to the MFP CLK input
refers to the timer clock signal, regardless of
5%, GND = 0Vdc, T
Characteristic
A
= 0 C to 70 C)
MK689 01-4
Min.
1.05
1.05
110
250
350
500
500
500
500
80
2
5. CS is latched internally, therefore if spec’s 1 and 24 are
6. Although CS and DTACK are synchronized with the
7. Spec. 30 applies to timer outputs TAO and TBO only.
Max.
1000
380
550
800
800
440
490
80
met then CS may be reasserted before the rising clock
and still terminate the current bus cycle.The new bus cy-
cle will be delayed by the MK68901 until all appropriate
internal operations have completed.
clock, the data out during a read cycle is asynchronous
to the clock, relying only on CS for timing.
Value
MK689 01-5
Min.
0.95
0.95
200
325
450
450
450
450
1.8
90
70
Max.
1000
380
550
800
800
420
370
80
T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL K
s
s
s
Fig.
29
29
30
25
28
27
27
27
27
28
28
28
28
27
27
27
29
28
Note
2