VN16118L1 VAISH [Vaishali Semiconductor], VN16118L1 Datasheet - Page 9

no-image

VN16118L1

Manufacturer Part Number
VN16118L1
Description
Gigabit Ethernet Transceiver
Manufacturer
VAISH [Vaishali Semiconductor]
Datasheet
VN16118
Table 8. Receiver Timing Characteristics
TA = 0 C to +70 C, Vcc = 3.15 V to 3.45 V
Notes:
1. This is the recovery for input phase jumps.
2. The receiver latency as shown in Figure 6, is defined as the time between receiving the first serial bit of a
1999-12-15
b_sync
f_lock
t
t
t
t
T_rxlat
SETUP
HOLD
DUTY
A-B
Symbol
RX_CLK<1>
RX_CLK<0>
parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel
word (defined by the rising edge of the receive byte clock, either RBC1 or RBC0).
COM_DET
Vaishali Semiconductor
[2]
RX<9:0>
[1]
RX_CLK<1>/<0>
RX<9:0>
DIN
Bit Sync Time
Frequency Lock at Powerup
Data Setup Before Rising Edge of RX_CLK
Data Hold After Rising Edge of RX_CLK
RX_CLK Duty Cycle
RX_CLK Skew
Receiver Latency
t
SETUP
R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
DATA BYTE C
l
747 Camden Avenue
K28.5
Figure 5. Receiver Section Timing
Parameter
t
HOLD
DATA
Figure 6. Receiver Latency
l
Campbell
DATA BYTE A
DATA BYTE D
Page 9
DATA
l
CA 95008
t_rxlat
l
DATA
Ph. 408.379.2900
2.5
1.5
40
7.5
Min.
t
A-B
DATA
22.4
28.0
Typ.
l
DATA BYTE D
Fax 408.379.2937
R2 R3 R4 R5
2500
500
60
8.5
Max.
bits
nsec
nsec
%
nsec
nsec
bits
Unit
s
Preliminary
2.0 V
0.8 V
2.0 V
0.8 V
1.4 V
1.4 V
MDSN-0001-00
1.4 V

Related parts for VN16118L1