VN16218L2 VAISH [Vaishali Semiconductor], VN16218L2 Datasheet

VN16218L2

Manufacturer Part Number

VN16218L2

Description

2.5 Gigabit SERDES Transceiver

Manufacturer

VAISH [Vaishali Semiconductor]

Datasheet

1.VN16218L2.pdf (11 pages)

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Applications

General Description

The VN16218 is a low power single chip, 2.5GBd transceiver. It provides a 2.5GBd serial link interface in

the physical layer and includes a Serialize/Deserialize (SERDES) capability. Other functions include clock

generation, clock data recovery, and word synchronization. In addition, an internal loopback function is

provided for system debugging.

The VN16218 is ideal for 2.5 Gigabit, serial backplane and proprietary point-to-point applications. The

device supports both fiber-optic and copper media.

The transmitter section of the VN16218 accepts 20-bit wide TTL data and latches it on the rising edge of the

incoming Transmit Byte Clock (TBC) and serializes the data onto the TX differential outputs, at a baud rate

that is twenty times the TBC frequency. The data is converted to a high-speed serial data stream. The

transmit PLL locks to the 125 MHz TBC. This clock is then multiplied by 20 to supply a 2.5 GHz serial clock

for parallel-to-serial conversion. The high-speed serial outputs can interface directly with copper cables or

PCB traces. Where optical transmission is required, the outputs can connect to a separate optical module.

When copper lines are the medium, equalization is available for improved performance.

The receiver section of the VN16218 accepts a serial data stream of 2.5 GBd and recovers 20 bit parallel

data. The receiver PLL locks on to the incoming serial signal and recovers the high-speed incoming clock

and data. The serial data is converted back into 20-bit parallel data format. Byte alignment is accomplished

by optional recognition of the K28.5+ comma character.

The recovered parallel data is sent to CMOS outputs, together with two 125 MHz clocks, RBC and RBCN,

that are 180 degrees out of phase from each other.

2001-11-09

Features

20-bit wide parallel Tx, Rx busses

20-bit LVTTL interface for transmit and

receive data at 125 MHz

125 MHz complementary receive and

byte clocks

Low Power Consumption

ESD rating >2000V (Human Body Model)

or >200V (Machine Model)

Vaishali Semiconductor

Fast serial backplane transceiver

747 Camden Avenue, Suite C

www.vaishali.com

Page 1

Campbell

2.5 Gigabit SERDES Transceiver

CA 95008

High-speed point-to-point links

Parallel loopback mode

Available in 14 mm x 14 mm

LQFP package

Differential PECL serial output

I/O power supply 3.3V

Core power supply 1.8 V

Ph. 408.377.6060

Advance Information

MDSN-0003-00

Fax 408.377.6063

VN16218

Related parts for VN16218L2

VN16218L2 Summary of contents

Page 1

Applications = Fast serial backplane transceiver General Description The VN16218 is a low power single chip, 2.5GBd transceiver. It provides a 2.5GBd serial link interface in the physical layer and includes a Serialize/Deserialize (SERDES) capability. Other functions include clock generation, ...

Page 2

VN16218 Figure 1. Functional Block Diagram T[0:19] TBC/REF (125 MHz) R[0:19] RCLK (125MHz) Comma Detect Figure 2. Pin Configuration ...

Page 3

VN16218 Table 1. Pin Description Name Pin # Type VDDT VSS 7, 30, 41 VDD 13, 31, 46 VDDA 21, 66, 69 TX[0:19 I-TTL 9,11, 14 16, 18, ...

Page 4

VN16218 Name Pin # Type RX[0:19] 65, 63, 59 O-TTL 57, 55, 52 50, 48, 45 43, 64 ,62 58, 56, 54 51,49,47 44, 42 RX+, RX- 68, 67 I-diff TX+, TX- 74 diff VDDP 76,78 P VSSP ...

Page 5

VN16218 Equalizer When EQEN is HIGH, the equalizer at the receiver is enabled, in order to correct for the frequency response of the cable or other system components. The equalizer compensates for distortion introduced by the cable, in order to ...

Page 6

VN16218 COM_DET Figure 3. Detection of a Properly Aligned Comma Character Figure 4. Detection and Resynchronization of an Improperly Aligned Comma Character Table 3. Absolute Maximum Ratings Symbol Parameter VDDT 3.3V Supply voltage VDD 1.8V Power Supply voltage V Differential ...

Page 7

VN16218 Table 4. Guaranteed Operating Rates +70 C, VDDT = 3. 3.45 V, VDD = 1.7V to 1.9V A Parallel Clock Rate (MHz) Serial Baud Rate (GBd) Min. Max. 124.0 126.0 ...

Page 8

VN16218 Table 10. DC Electrical Specifications for LVTTL Inputs +70 C, VDDT = 3. 3.45 V. VDD = 1.7V to 1.9V A Symbol Parameter V Input High Voltage Level IH V Input Low ...

Page 9

VN16218 Table 12. Receiver Timing Characteristics +70 C, Vcc = 3. 3.45 V Symbol Parameter [1] b_sync Bit Sync Time f_lock Frequency Lock at Powerup t Data Setup Before Rising Edge of RBC,RBCN ...

Page 10

VN16218 Serial Input Rise and Fall Time V IHD V ILD T r Figure 9. Parametric Measurement Information Amplitude Figure 10. Receiver Input Eye Jitter Tolerance Mask Diagram Serial Output Load RX+, RX Figure 11. ...

Page 11

... Figure 12. Mechanical Dimensions 80 Pin LQFP All dimensions are in millimeters D1/ 0.3 0.65 1.0 Package follows JEDEC Standards Ordering Information Part Number Marking Shipping/Packaging VN16218L2 VN16218L2 Trays 2001-11-09 Vaishali Semiconductor 747 Camden Avenue, Suite C A1 stand-off A2 body thickness L1 lead length b lead width c lead thickness e lead pitch ...

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