PLL202-151 PhaseLink (PLL), PLL202-151 Datasheet - Page 3

• Manufacturer Part Number: PLL202-151
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS (Continue)
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CPU[T,C]/
CPU0D_[T,C]
PCI_F/FS1
48MHz/FS3
PCI0/
SEL_SDR_DDR
PCI[2:5]
24_48MHz/FS2
AGP0_ZCLK/SEL_V
IA
AGP2
Iref
SDATA
SCLK
SD#//WDRESET#
BUF_IN
FB_OUT
Name
Programmable Clock Generator for VIA, ALI and SIS DDR SYSTEM
14,15,17,18
Number
52,53
10
20
11
21
25
28
27
26
45
46
6
8
Type
O
O
O
O
B
B
B
B
B
B
B
I
I
I
In P4 mode, these two pins are differential signals of CPUT and CPUC
In K7 mode, these two pins are differential open drain outputs of CPUODT
and CPUODC.
Bi-directional pin. At power-up, the FS1 input value is latched. After
power-up, this pin acts as PCI_F output. It has an internal pull-down and a
20 ohm on-chip series resistor.
Bi-directional pin. At power-up, the FS3 input value is latched. After
power-up, this pin acts as 48MHz output. It has an internal pull-down and
a 20 ohm on-chip series resistor.
Bi-directional pin. At power-up, the SEL_SDR_DDR input value is latched.
After power-up, this pin acts as PCI0 output. It has an internal pull-down
and a 20 ohm on-chip series resistor.
If SEL_SDR_DDR=0, DDR mode is selected
If SEL_SDR_DDR=1, SDRAM mode is selected.
PCI clock output (see Frequency table) with a 20 ohm on-chip series
resistor. PCI5 has I2C programmable double drive strength.
Bi-directional pin. At power-up, the FS2 input value is latched. After
power-up, this pin acts as 24_48MHz output. It has an internal pull-up and
a 20 ohm on-chip series resistor. The selection of 24_48MHz is via I2C on
Byte3 bit6. It will generate 48MHz as power on default.
Bi-directional pin. At power-up, the SEL_VIA input value is latched. After
power-up, this pin acts as AGP0_ZCLK clock output. It has an internal
pull-down and a 20 ohm on-chip series resistor with I2C programmable
double drive strength.
If SEL_VIA=0, VIA mode is selected.
If SEL_VIA=1, ALI_SIS mode is selected.
AGP2 clock output. It has a 20 ohm on-chip series resistor.
This pin establishes the reference current for the CPU differential pairs, it
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
Serial data inputs for serial interface port.
Serial data inputs for serial interface port.
When Byte 10 bit 7 is 1, this pin generates Watchdog timer reset signal
after timer expires. By default, this input pin acts as Slow Down function to
smoothly reduce output frequency by 15~30% depends on internal VCO
divider when SD#=0.
In VIA mode, 3.3V CMOS input for SDRAM mode; 2.5V input for DDR
mode.
In ALI_SIS mode, this input should be connected to ground.
Feedback clock for chipset. Output voltage depends on VDDD.
PRELIMINARY
Description
PLL202-151
Rev 11/05/01 Page 3