dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 3

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

7. EEPROM Format............................................................................................................................................................. 28
8. PHY Register Description ................................................................................................................................................ 29
Final
Version: DM9000A-17-DS-F01
May 10, 2006
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode).................................................................................................... 20
6.16 Physical Address Register ( 10H~15H ) .................................................................................................................... 20
6.17 Multicast Address Register ( 16H~1DH ) .................................................................................................................. 20
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H) .................... 20
6.19 General purpose Register ( 1FH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H) ................................... 22
6.20 TX SRAM Read Pointer Address Register (22H~23H) .............................................................................................. 22
6.21 RX SRAM Write Pointer Address Register (24H~25H).............................................................................................. 22
6.22 Vendor ID Register (28H~29H) ................................................................................................................................. 22
6.23 Product ID Register (2AH~2BH)............................................................................................................................... 22
6.24 Chip Revision Register (2CH) ................................................................................................................................... 22
6.25 Transmit Control Register 2 ( 2DH ) ......................................................................................................................... 22
6.26 Operation Test Control Register ( 2EH ) ................................................................................................................... 23
6.27 Special Mode Control Register ( 2FH ) ..................................................................................................................... 23
6.28 Early Transmit Control/Status Register ( 30H )......................................................................................................... 24
6.29 Check Sum Control Register ( 31H ).......................................................................................................................... 24
6.30 Receive Check Sum Status Register ( 32H )............................................................................................................... 24
6.31 MII PHY Address Register ( 33H )............................................................................................................................. 25
6.32 LED Pin Control Register ( 34H ) ............................................................................................................................. 25
6.33 Processor Bus Control Register ( 38H ) .................................................................................................................... 25
6.34 INT Pin Control Register ( 39H )............................................................................................................................... 26
6.35 System Clock Turn ON Control Register ( 50H ) ....................................................................................................... 26
6.36 Resume System Clock Control Register ( 51H )......................................................................................................... 26
6.37 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ............................................. 26
6.38 Memory Data Read Command without Address Increment Register (F1H) .............................................................. 26
6.39 Memory Data Read Command with Address Increment Register (F2H) ................................................................... 26
6.40 Memory Data Read_address Register (F4H~F5H) ................................................................................................... 26
6.41 Memory Data Write Command without Address Increment Register (F6H).............................................................. 26
6.42 Memory data write command with address increment Register (F8H) ..................................................................... 27
6.43 Memory data write_address Register (FAH~FBH).................................................................................................... 27
6.44 TX Packet Length Register (FCH~FDH)................................................................................................................... 27
6.45 Interrupt Status Register (FEH)................................................................................................................................. 27
6.46 Interrupt Mask Register (FFH).................................................................................................................................. 27
Ethernet Controller with General Processor Interface
DM9000A
3