dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 25

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

6.31 MII PHY Address Register ( 33H )
6.32 LED Pin Control Register ( 34H )
6.33 Processor Bus Control Register ( 38H )
Final
Version: DM9000A-17-DS-F01
May 10, 2006
6~5
4~0
7:2
7:5
Bit
Bit
Bit
7
1
0
4
3
2
1
0
IOW_SPIKE
EPHYADR
IOR_SPIKE
Reserved
Reserved
ADR_EN
CURR
Name
Name
Name
Reserved
Reserved
GPIO
EST
MII
HPS0,RO Reserved
HPS01,R
HPS0,R
Default
P011,RW
PS0,RO
Default
Default
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P1,RW
W
W
External PHY Address Enabled
When register 34H bit 0 is set to ‘1’, the PHY address field in MII Management
Interface format is defined at bit 4~0.
External PHY Address Bit 4~0
The PHY address field in MII Management Interface format.
Reserved
LED act as General Purpose signals in 16-bit mode
1: Pin 38/39 (LED2/1) act as the general purpose pins that are controlled by
registers 1Eh bit 2/1 and 1Fh bit 2/1 respectively.
LED act as SMI signals in 16-bit mode
1: Pin 38/39 (LED2/1) act as the MII Management Interface mode.
Data Bus Current Driving/Sinking Capability
000: 2mA
001: 4mA
010: 6mA
011: 8mA (default)
100: 10mA
101: 12mA
110: 14mA
111: 16mA
Reserved
Enable Schmitt Trigger
1: Pin 35/36/37 (IOR/IOW/CS#) have Schmitt trigger capability.
Reserved
Eliminate IOW spike
1: eliminate about 2ns IOW spike
Eliminate IOR spike
1: eliminate about 2ns IOR spike
In this mode, the LED1 act as data (MDIO) signal and the LED2 act as sourced
These two pin are controlled by registers 0Bh,0Ch, and 0Dh.
clock (MDC) signal.
Ethernet Controller with General Processor Interface
Description
Description
Description
DM9000A
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