dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 17

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

6.8 Receive Overflow Counter Register ( 07H )
6.9 Back Pressure Threshold Register (08H)
6.10 Flow Control Threshold Register ( 09H )
Final
Version: DM9000A-17-DS-F01
May 10, 2006
6:0
Bit
7:4
3:0
7:4
Bit
Bit
7
1
0
Name
RXFU
ROC
BPHW
HWOT
Name
Name
FOE
JPT
CE
PS0,R/C
PS0,R/C
Default
PS3, RW
PS7, RW
PS3, RW
PS0,RO
PS0,RO
Default
Default
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
The default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space. The
default value is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K
bytes)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ethernet Controller with General Processor Interface
100us
150us
200us
250us
300us
350us
400us
450us
500us
550us
600us
time
10us
15us
25us
50us
5us
Description
Description
Description
DM9000A
17