dm9000a Davicom Semiconductor, Inc., dm9000a Datasheet - Page 24

• Manufacturer Part Number: dm9000a
• Description: Ethernet Controller With General Processor Interface
• Manufacturer: Davicom Semiconductor, Inc.

6.28 Early Transmit Control/Status Register ( 30H )
6.29 Check Sum Control Register ( 31H )
6.30 Receive Check Sum Status Register ( 32H )
Final
Version: DM9000A-17-DS-F01
May 10, 2006
4~2
1~0
7~3
Bit
Bit
Bit
7
6
5
2
1
0
7
6
5
4
3
2
1
0
RESERVED
RESERVED
UDPCSE
TCPCSE
RCSEN
IPCSE
Name
Name
Name
UDPS
UDPP
DCSE
TCPS
TCPP
ETS2
ETS1
ETE
ETT
IPS
IPP
PS0, RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RW
PS0,RO
PS0,RO
PS0,RO
PS0,RO
PS0,RO
PS0,RO
PS0,RO
PS0,RO
000,RO
Default
Default
Default
0,RO
Early Transmit Enable
Enable bits[2:0]
Early Transmit Status II
Early Transmit Status I
Reserved
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
----- ----
0
0
1
1
Reserved
UDP CheckSum Generation Enable
TCP CheckSum Generation Enable
IP CheckSum Generation Enable
UDP CheckSum Status
1: checksum fail, if UDP packet
TCP CheckSum Status
1: checksum fail, if TCP packet
IP CheckSum Status
1: checksum fail, if IP packet
UDP Packet
TCP Packet
IP Packet
Receive CheckSum Checking Enable
When set, the checksum status (bit 7~2) will be stored in packet’s first byte(bit
7~2) of status header respectively.
Discard CheckSum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
0
1
0
1
: 12.5%
: 25%
: 50%
: 75%
threshold
-------------
Ethernet Controller with General Processor Interface
Description
Description
Description
DM9000A
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