SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 488
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SC9S12XS256J1MAA
Manufacturer Part Number
SC9S12XS256J1MAA
Description
HCS12 Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.SC9S12XS256J1MAA.pdf
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Voltage Regulator (S12VREGL3V3V1)
17.1.3
Figure 17-1
REG consists of three parallel subblocks, REG1, REG2 and REG3, providing three independent output
voltages.
488
3. Shutdown mode
Controlled by VREGEN (see device level specification for connectivity of VREGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in a high-
impedance state, only the POR feature is available, LVD, LVR and HTD are disabled. The API
internal RC oscillator clock is not available.
This mode must be used to disable the chip internal regulator VREG_3V3, i.e., to bypass the
VREG_3V3 to use external supplies.
Block Diagram
shows the function principle of VREG_3V3 by means of a block diagram. The regulator core
S12XS Family Reference Manual, Rev. 1.09
Freescale Semiconductor
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