SC9S12XS256J1MAA FREESCALE [Freescale Semiconductor, Inc], SC9S12XS256J1MAA Datasheet - Page 127

• Manufacturer Part Number: SC9S12XS256J1MAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

3.1.3
The S12X architecture implements a number of memory mapping schemes including
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1
3.1.4.2
3.1.5
Figure 3-1
Freescale Semiconductor
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a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
Single chip modes
In normal and special single chip mode the internal memory is used.
S12X Memory Mapping
Modes of Operation
Block Diagram
shows a block diagram of the MMC.
Power Saving Modes
Functional Modes
S12XS Family Reference Manual, Rev. 1.09
Memory Mapping Control (S12XMMCV4)
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